Gate dielectric antifuse circuit to protect a high-voltage transistor
First Claim
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1. An antifuse circuit, comprising:
- a bus;
an antifuse including a first node connected to the bus;
a transistor connected to the antifuse, the transistor including a gate; and
a gate control circuit connected to the gate, wherein the gate control circuit includes a first impedance connected to the bus and the gate and a second impedance connected between a supply voltage and the gate.
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Abstract
According to embodiments of the present invention, circuits have elements to protect a high-voltage transistor in a gate dielectric antifuse circuit. An antifuse has a layer of gate dielectric between a first terminal coupled to receive an elevated voltage and a second terminal, and a high-voltage transistor is coupled to the antifuse and has a gate terminal. An intermediate voltage between the supply voltage and the elevated voltage is coupled to the gate terminal of the high-voltage transistor to protect the high-voltage transistor.
58 Citations
20 Claims
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1. An antifuse circuit, comprising:
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a bus; an antifuse including a first node connected to the bus; a transistor connected to the antifuse, the transistor including a gate; and a gate control circuit connected to the gate, wherein the gate control circuit includes a first impedance connected to the bus and the gate and a second impedance connected between a supply voltage and the gate. - View Dependent Claims (2, 3, 4, 5, 6, 7)
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8. An antifuse circuit, comprising:
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a bus; an antifuse including a first node connected to the bus; a high voltage, first transistor connected to the antifuse, the first transistor including a gate; a gate control circuit connected to the gate, wherein the gate control circuit includes a first impedance connected to the bus and the gate and a second impedance connected between a supply voltage and the gate; and a second transistor coupled to the high-voltage, first transistor to control current flowing through the antifuse and the high-voltage, first transistor. - View Dependent Claims (9, 10, 11, 12, 13)
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14. An antifuse circuit, comprising:
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a bus; an antifuse including a first node connected to the bus; a high voltage, first transistor including a first source/drain connected to the antifuse, the first transistor including a gate; a gate control circuit connected to the gate, wherein the gate control circuit includes a first impedance connected to the bus and the gate and a second impedance connected between a supply voltage and the gate; and a read circuit coupled to the high-voltage transistor to read the antifuse during an active mode. - View Dependent Claims (15, 16, 17, 18, 19, 20)
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Specification