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Versatile semiconductor test structure array

  • US 7,405,585 B2
  • Filed: 09/15/2006
  • Issued: 07/29/2008
  • Est. Priority Date: 02/14/2006
  • Status: Active Grant
First Claim
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1. A semiconductor test structure array comprising:

  • a plurality of unit cells containing devices under test (DUTs) arranged in an addressable array, each device under test including a plurality of pins for receiving test signals; and

    an access-control circuitry within each unit cell for controlling accesses to the one or more DUTs,wherein the access-control circuitry comprises at least two identical controlled transmission gates (CTGs), each CTG being turned on simultaneously to pass the test signals to a given device under test and a plurality of the access-control circuitries are isomorphic.

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