Versatile semiconductor test structure array

• US 7,405,585 B2
• Filed: 09/15/2006
• Issued: 07/29/2008
• Est. Priority Date: 02/14/2006
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Doong, Yih-Yuh
• Primary Examiner(s): Nguyen; Ha
• Assistant Examiner(s): Benitez; Joshua
• Application Number:
  US11/522,069
• Publication Number:
  US 20070200587A1
• Time in Patent Office: 683 Days
• Field of Search: 324/158.1, 324/763, 324/767, 324769-770, 365/201, 714733-734
• US Class Current: 324/750.3
• CPC Class Codes: G01R 31/31722 Addressing or selecting of test units, e.g. transmission protocols for selecting test units for scan test G01R31/318558
• CPC Class Codes: G01R 31/31723 Hardware for routing the test signal within the device under test to the circuits to be tested, e.g. multiplexer for multiple core testing, accessing internal nodes routing the test signal to or from the device under test G01R31/31926

Abstract

This invention discloses a semiconductor test structure array comprising a plurality of unit cells for containing devices under test (DUT) arranged in an addressable array, and an access-control circuitry within each unit cell for controlling accesses to one or more DUTs, wherein the access-control circuitry comprises at least four identical controlled transmission gates (CTGs), and a plurality of the access-control circuitries are isomorphic.

Claims

1. A semiconductor test structure array comprising:

a plurality of unit cells containing devices under test (DUTs) arranged in an addressable array, each device under test including a plurality of pins for receiving test signals; and

an access-control circuitry within each unit cell for controlling accesses to the one or more DUTs,

wherein the access-control circuitry comprises at least two identical controlled transmission gates (CTGs), each CTG being turned on simultaneously to pass the test signals to a given device under test and a plurality of the access-control circuitries are isomorphic.

2. The semiconductor test structure array of claim 1, wherein at least one CTG further comprises one or more NMOS transistors and one or more PMOS transistors connected as a transmission gate.

3. The semiconductor test structure array of claim 2, wherein the NMOS and the PMOS transistors have predetermined channel width-over-length ratios to ensure both the NMOS and the PMOS transistors operate in linear regions for a given device under test.

4. The semiconductor test structure array of claim 1, wherein at least one CTG further comprises one or more NMOS transistors connected as a transmission gate.

5. The semiconductor test structure array of claim 4, wherein the NMOS transistors have predetermined channel width-over-length ratios to ensure the NMOS transistors operate in linear regions for a given device under test.

6. The semiconductor test structure array of claim 1, wherein at least one CTG further comprises one or more PMOS transistors connected as a transmission gate.

7. The semiconductor test structure array of claim 6, wherein the PMOS transistors have predetermined channel width-over-length ratios to ensure the PMOS transistors operate in linear regions for a given device under test.

8. The semiconductor test structure array of claim 1 further comprising a row decoder and a column decoder for addressing the unit cells.

9. The semiconductor test structure array of claim 1, wherein the number of CTGs in an access-control circuitry is at least four.

10. The semiconductor test structure array of claim 1, wherein each access-control circuitry further comprises one or more address pins to simultaneously control the CTGs contained therein.

11. The semiconductor test structure array of claim 1, wherein the corresponding CTGs in a plurality of unit cells of a row are coupled to a row data-line.

12. The semiconductor test structure array of claim 1, wherein the corresponding CTGs in a plurality of unit cells of a column are coupled to a column data-line.

13. A semiconductor test structure array comprising:

a plurality of unit cells containing devices under test (DUTs) arranged in an addressable array, each device under test including a plurality of pins for receiving test signals; and

an access-control circuitry within each unit cell for controlling accesses to the one or more DUTs,

wherein the access-control circuitries are isomorphic and each access-control circuitry comprises at least two identical controlled transmission gates (CTGs), and each CTG being turned on simultaneously to pass the test signals to a given device under test, and

wherein at least one of the CTGs further comprises one or more NMOS transistors and one or more PMOS transistors connected as a transmission gate, wherein the NMOS and the PMOS transistors have predetermined channel width-over-length ratios to ensure both the NMOS and the PMOS transistors operate in linear regions for a given device under test.

14. The semiconductor test structure array of claim 13 further comprising a row decoder and a column decoder for addressing the unit cells.

15. The semiconductor test structure array of claim 13, wherein the number of CTGs in an access-control circuitry is at least four.

16. The semiconductor test structure array of claim 13, wherein the each access-control circuitry further comprises one or more address pins to simultaneously control the CTGs contained therein.

17. The semiconductor test structure array of claim 13, wherein the corresponding CTGs in a plurality of unit cells of a row are coupled to a row data-line.

18. The semiconductor test structure array of claim 13, wherein the corresponding CTGs in a plurality of unit cells of a column are coupled to a column data-line.

19. A semiconductor test structure array comprising:

a row decoder;

a column decoder;

a plurality of unit cells containing devices under test (DUTs) arranged in an addressable array, each device under test including a plurality of pins for receiving test signals; and

an access-control circuitry within each unit cell for controlling accesses to the one or more DUTs,

wherein the access-control circuitries are isomorphic and each access-control circuitry comprises at least two identical controlled transmission gates (CTGs), each CTG being turned on simultaneously to pass the test signals to a given device under test, and

wherein the CTG further comprises one or more NMOS transistors and one or more PMOS transistors connected as a transmission gate, wherein the NMOS and the PMOS transistors have predetermined channel width-over-length ratios to ensure both the NMOS and the PMOS transistors operate in linear regions for a given device under test.

20. The semiconductor test structure array of claim 19, wherein each access-control circuitry farther comprises one or more address pins to simultaneously control the CTGs contained therein.