RFID tag switched capacitor slicer threshold

• US 7,405,659 B1
• Filed: 01/26/2006
• Issued: 07/29/2008
• Est. Priority Date: 03/31/2004
• Status: Active Grant

• Current Assignee: Impinj, Inc.
• Original Assignee: Impinj, Inc.
• Inventors: Hyde, John D.
• Primary Examiner(s): Bugg; George A
• Assistant Examiner(s): Previl; Daniel
• Application Number:
  US11/340,033
• Time in Patent Office: 915 Days
• Field of Search: 340/10.4, 340/10.1, 340/10.2, 340/572.2, 340/572.4, 340/825.69, 340/825.72, 340/10.51, 340/572.1, 340/10.5, 340/10.34, 235/462, 235/436
• US Class Current: 340/572.4
• CPC Class Codes: G06K 19/0723 the record carrier comprising an arrangement for non-contact communication, e.g. wireless communication circuits on transponder cards, non-contact smart cards or RFIDs

Abstract

An RFID tag that receives an RF signal from a reader is arranged to derive a threshold signal from a detected envelope of the RF signal, where the threshold signal is proportional to the detected envelope signal. The detected envelope signal is then compared to the threshold signal to derive a digital signal from the received RF signal. By maintaining the threshold signal proportional to the detected envelope signal, false bit detections due to ripple effect on the received signal and interference from other sources are reduced. The threshold signal may be derived employing a switched capacitor attenuator circuit.

Claims

1. A demodulator circuit for an RFID tag, comprising:

an envelope detector for deriving a first signal responsive to detecting an envelope of a received signal;

an attenuator for attenuating a portion of the first signal to derive a second signal by repetitively charging a capacitor of the attenuator with the first signal, and then discharging the capacitor;

a peak detector for deriving a threshold signal by detecting a peak of the second signal, wherein the threshold signal is proportional to the first signal; and

a comparator for providing a digital signal in response to comparing the first signal and the threshold signal.

2. The demodulator circuit of claim 1, wherein

the attenuator is a switched capacitor attenuator configured to derive the second signal by repetitively charging a capacitor with the first signal, and then discharging the capacitor.

3. The demodulator circuit of claim 2, wherein

the capacitor is discharged completely.

4. The demodulator circuit of claim 2, wherein

the switched capacitor attenuator includes a second capacitor, and discharging redistributes charge to the second capacitor.

5. The demodulator circuit of claim 2, wherein

the switched capacitor attenuator further includes a reset switch configured to discharge the capacitor in response to a reset signal.

6. The demodulator circuit of claim 2, wherein

the capacitor is adapted to be charged and discharged responsive to a clock signal.

7. The demodulator circuit of claim 6, wherein

charging and discharging are performed in response to a first trigger signal and a second trigger signal that are derived from the clock signal such that a high value of the first trigger signal and a high value of the second trigger signal do not overlap.

8. The demodulator circuit of claim 7, wherein

the switched capacitor attenuator includes:

a first switch coupled between a first node and a second node such that the first signal is received at the first node, and the first switch is actuated by the first trigger signal corresponding to a sampling phase;

a second switch coupled between the second node and a low supply voltage, and actuated by the second trigger signal corresponding to a holding phase;

a sampling capacitor coupled between the second node and a third node;

a third switch coupled between the third node and the low supply voltage, and actuated by the second trigger signal such that the second switch and the third switch are arranged to shunt the sampling capacitor in response to the second trigger signal; and

a holding capacitor coupled between the third node and the low supply voltage.

9. The demodulator circuit of claim 8, further comprising:

a fourth switch coupled between the third node and a fourth node such that the threshold signal is provided at the fourth node, and the fourth switch is actuated by the first trigger signal;

a filtering capacitor coupled between the fourth node and the low supply voltage such that the third capacitor acts as a low-pass filter.

10. The demodulator circuit of claim 8, wherein

a capacitance of the sampling capacitor and a capacitance of the holding capacitor define a gain of the switched capacitor attenuator, and

a peak of the threshold signal is determined from the gain.

11. The demodulator circuit of claim 2, wherein

the switched capacitor attenuator is configured to:

charge a first sampling capacitor and a second sampling capacitor by actuating a first sampling switch and a second sampling switch;

transfer the charges in the first sampling capacitor and the second sampling capacitor to a holding capacitor by actuating a first holding switch and a second holding switch; and

discharge the first sampling capacitor and the second sampling capacitor by actuating a first discharging switch and a second discharging switch.

12. The demodulator circuit of claim 11, wherein

the switched capacitor attenuator is further configured to:

filter the attenuated portion of the first signal employing a filter switch and a filter capacitor acting as a low-pass filter.

13. The demodulator circuit of claim 11, wherein

the first sampling switch, the second sampling switch, the first holding switch, the second holding switch, and the filter switch are actuated by a first trigger signal;

and

the first discharging switch and the second discharging switch are actuated by a second trigger signal.

14. The demodulator circuit of claim 13, wherein

the switched capacitor attenuator is further configured to:

charge a third sampling capacitor by actuating a third sampling switch;

transfer the charges in the third sampling capacitor to the holding capacitor by actuating a third holding switch; and

discharge the third sampling capacitor by actuating a third discharging switch; and

wherein the third sampling switch and the third holding switch are actuated by the first trigger signal, and the third discharge switch is actuated by the second trigger signal.

15. The demodulator circuit of claim 1, further comprising:

a leak current circuit adapted to provide a low droop rate to track a fading of the analog signal.

16. The demodulator circuit of claim 1, wherein

the attenuator is a resistive attenuator.

17. A demodulator circuit for an RFID tag, comprising:

a means for deriving a first signal responsive to detecting an envelope of a received signal;

a means for attenuating at least a portion of the first signal to derive a second signal;

a means for deriving a threshold signal by detecting a peak of the second signal, wherein the threshold signal is proportional to the first signal; and

a means for deriving a digital signal by comparing the first signal and the threshold signal.

18. The RFID tag of claim 17, wherein

the means for attenuating at least a portion of the first signal is configured to derive the second signal by repetitively charging a capacitive circuit with the first signal, and then discharging the capacitive circuit.

19. A method for a demodulator circuit in an RFID tag, comprising:

deriving a first signal responsive to detecting an envelope of a received signal;

attenuating at least a portion of the first signal to derive a second signal;

deriving a threshold signal by detecting a peak of the second signal, wherein the threshold signal is proportional to the first signal; and

deriving a digital signal by comparing the first signal and the threshold signal.

20. The method of claim 19, wherein

attenuating at least a portion of the first signal includes repetitively charging a capacitive circuit with the first signal, and then discharging the capacitive circuit.

21. The method of claim 20, wherein

a capacitance of at least one capacitor of the capacitive circuit defines a gain of the capacitive circuit, and

a peak of the threshold signal is determined from the gain.

22. The method of claim 20, wherein

charging and discharging are performed in response to a clock signal.

23. The method of claim 22, wherein

charging and discharging are performed in response to a first trigger signal and a second trigger signal that are derived from the clock signal.

24. The method of claim 23, wherein

charging and discharging the capacitive circuit includes:

actuating a first and a fourth switch of the capacitive circuit by the first trigger signal corresponding to a sampling phase; and

actuating a second and a third switch of the capacitive circuit by the second first trigger signal correspond to a holding phase such that a high value of the first trigger signal and a high value of the second trigger signal do not overlap.

25. The method of claim 19, further comprising:

low-pass filtering the second signal.