Delta-sigma analog digital converter with offset compensation

• US 7,405,682 B2
• Filed: 01/22/2007
• Issued: 07/29/2008
• Est. Priority Date: 01/30/2006
• Status: Active Grant

• Current Assignee: National Semiconductor Germany AG (Texas Instruments, Inc.)
• Original Assignee: National Semiconductor Germany AG (Texas Instruments, Inc.)
• Inventors: Ebner, Christian, Mitteregger, Gerhard
• Primary Examiner(s): Mai; Lam T
• Application Number:
  US11/656,056
• Publication Number:
  US 20070216557A1
• Time in Patent Office: 554 Days
• Field of Search: 341115-155
• US Class Current: 341/120
• CPC Class Codes: H03M 3/384 Offset correction removal of offset already present on the analogue input signal H03M3/494
• CPC Class Codes: H03M 3/424 the quantiser being a multiple bit one
• CPC Class Codes: H03M 3/454 with distributed feedback, i.e. with feedback paths from the quantiser output to more than one filter stage

Abstract

The invention concerns a time-continuous delta-sigma analog-digital converter for the conversion of an analog input signal into a digital output signal, comprising an analog filter for the filtering of the analog input signal, a clocked operated quantiser, which contains at least one comparator (34) and which quantises the filtered analog signal outputted through the analog filter for the generation of the digital output signal, and a feedback arrangement with at least one digital-analog converter, which supplies to the analog filter at least one feedback signal on the basis of the digital output signal. According to the invention a calibration device (32) linked with the quantiser is stipulated, which is designed to determine at a predetermined point in time an offset error of the comparator (34) and subsequently to compensate for this (Itrim).

Claims

1. A delta-sigma analog-digital converter (10) for the conversion of an analog input signal (Vin) into a digital output signal (Vout), comprising:

an analog filter (20) for the filtering of the analog input signal,

a quantiser (30) clocked by a clock signal (CLK), which comprises at least one comparator (34) and quantises the filtered analog signal outputted by the analog filter (20) for the generation of the digital output signal,

a feedback arrangement (40) with at least one digital-analog converter (DAC1, DAC2, DAC3), which supplies to the analog filter (20) at least one analog feedback signal on the basis of the digital output signal (Vout), and

a calibration device (32) linked with the quantiser (30), which is designed at a predetermined point in time to determine an offset error of the comparator (34) and subsequently to compensate for this.

2. The converter according to claim 1, wherein the converter is designed such that an operational start-up of the converter (10) is stipulated as the point in time for the determination of the offset error and its subsequent compensation.

3. The converter according to claim 1, wherein the calibration device is adapted to perform a calibration, including following steps:

application of a predetermined test signal (VCM, Itrim) at the input of the comparator (34),

evaluation of the reaction of the comparator (34) to the test signal, and

subsequent compensation of the offset error on the basis of the evaluation result.

4. The converter according to claim 1, wherein the calibration device is adapted to perform a calibration, including following steps:

application of a test signal (VCM, Itrim) corresponding to the comparator threshold at the input of the comparator (34),

determination of the decision of the comparator (34) in reaction to the test signal (VCM, Itrim),

variation of the test signal (VCM, Itrim) in order to determine that test signal magnitude, in what follows designated as the compensation signal (Itrim), at which the comparator (34) makes the opposite decision,

storage of the compensation signal for at least as long as until a renewed calibration takes place, or the operation of the converter (10) is interrupted, and

compensation of the offset error by additional application of the compensation signal (Itrim) to the comparator (34) during the converter operation.

5. The converter according to claim 1, wherein the calibration device is adapted to perform a calibration, including following steps:

application of a test signal (VCM, Itrim) corresponding to a particular decision of the comparator (34) at the input of the comparator (34),

variation of the test signal (VCM, Itrim) in order to determine that test signal magnitude, in what follows designated as the compensation signal (Itrim), at which the comparator (34) makes the opposite decision,

storage of the compensation signal for at least as long as until a renewed calibration takes place, or the operation of the converter (10) is interrupted, and

compensation of the offset error by additional application of the compensation signal (Itrim) to the comparator (34) during the converter operation.

6. The converter according to claim 4, wherein the variation of the test signal magnitude is provided as a monotonic variation until the comparator (34) tips over.

7. The converter according to claim 3, wherein the calibration device (32) generates the test signal (VCM, Itrim) digitally.

8. The converter according to claim 1, further comprising a full-differential design.

9. The converter according to claim 1, wherein the quantiser (30) has a plurality of quantising stages.

10. The converter according to claim 1, wherein the digital output signal (Vout) of the quantiser (30) possesses a thermometer code.