Semiconductor memory device, page buffer resource assigning method and circuit therefor, computer system and mobile electronic device

• US 7,405,974 B2
• Filed: 05/19/2004
• Issued: 07/29/2008
• Est. Priority Date: 05/20/2003
• Status: Expired due to Fees

• Current Assignee: Sharp Kabushiki Kaisha (Hon Hai Precision Industry Co., Ltd.)
• Original Assignee: Sharp Kabushiki Kaisha (Hon Hai Precision Industry Co., Ltd.)
• Inventors: Yaoi, Yoshifumi, Iwase, Yasuaki, Iwata, Hiroshi, Shibata, Akihide, Morikawa, Yoshinao, Nawaki, Masaru
• Primary Examiner(s): NGUYEN, TAN
• Application Number:
  US10/848,324
• Publication Number:
  US 20040268027A1
• Time in Patent Office: 1,532 Days
• Field of Search: 365/185.05
• US Class Current: 365/185.12
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 2207/2245 Memory devices with an internal cache buffer
• CPC Class Codes: G11C 7/10 Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
• CPC Class Codes: G11C 7/1039 using pipelining techniques, i.e. using latches between functional memory parts, e.g. row/column decoders, I/O buffers, sense amplifiers

Abstract

A semiconductor memory device includes a page buffer circuit and an arrangement of memory elements each including: a gate electrode provided on a semiconductor layer with an intervening gate insulating film; a channel region provided beneath the gate electrode; a diffusion area provided on both sides of the channel region, having an opposite polarity to the channel region; and a memory functioning member provided on both sides of the gate electrodes, having a function of storing electric charge. The page buffer circuit provides a common resource shared between a memory array controller and a user. The page buffer circuit has two planes containing random access memory arrays. The page buffer circuit also includes a mode control section to facilitate access to the planes over a main bus in user mode and access to the planes by the memory array controller in memory control mode.

Claims

1. A semiconductor memory device, comprising:

a memory array of memory elements each including;

a gate electrode provided on a semiconductor layer with an intervening gate insulating film;

a channel region provided beneath the gate electrode;

a diffusion area provided on both sides of the channel region, having an opposite polarity to the channel region; and

a memory functioning member provided on both sides of the gate electrodes, having a function of storing electric charge, the memory functioning member being formed by at least one of an insulating film including at least one conductor or semiconductor dot and an insulating film including a ferroelectric film in which inner charge of the ferroelectric film is polarized by an electric filed and in which the polarized state is held;

a page buffer circuit connected to a main bus via a first port and to an internal bus via a second port, containing multiple page planes;

an access control circuit operating either in a user mode or in a memory control mode as determined by a control signal, enabling access to the page planes over the main bus when in the user mode and over the internal bus when in the memory control mode;

an interface circuit connected to the main bus and the page buffer circuit, generating the control signal to assign the page planes to the user mode and the memory control mode in accordance with a command received over the main bus; and

a memory control circuit controlling at least write operation to the memory array, connected to the page buffer circuit over the internal bus and accessing the page buffer circuit in the memory control mode.

2. The semiconductor memory device as set forth in claim 1, wherein the interface circuit assigns a first one of the page planes to the user mode according to a rewrite page buffer continuous command in the command, receives a rewrite data block over the main bus, and transfers the rewrite data block to the first page plane.

3. The semiconductor memory device as set forth in claim 2, wherein the interface circuit, when having received the rewrite page buffer continuous command containing a program including a page buffer command, assigns the first page plane to the memory control mode according to the program.

4. The semiconductor memory device as set forth in claim 3, wherein the interface circuit, if a second one of the page planes is not assigned to the memory control mode, assigns the second page plane to the user mode.

5. The semiconductor memory device as set forth in claim 4, wherein the interface circuit, when having received a next rewrite page buffer continuous command and a next rewrite data block over the main bus, transfers the received next rewrite data block to the second page plane.

6. The semiconductor memory device as set forth in claim 1, wherein:

the page planes include a first page plane and a second page plane; and

the interface circuit assigns the second page plane to the user mode according to a rewrite page buffer continuous command in the command, receives a rewrite data block over the main bus, and transfers the rewrite data block to the second page plane.

7. The semiconductor memory device as set forth in claim 6, wherein the interface circuit, when having received the rewrite page buffer continuous command containing a program including a page buffer command, assigns the second page plane to the memory control mode according to the program.

8. The semiconductor memory device as set forth in claim 7, wherein the interface circuit, if the first page plane is not assigned to the memory control mode, assigns the first page plane to the user mode.

9. The semiconductor memory device as set forth in claim 1, wherein:

the page planes include a first page plane and a second page plane; and

the interface circuit swaps the user mode and the memory control mode between the first page plane and the second page plane according to a swap page buffer command in the command.

10. The semiconductor memory device as set forth in claim 1, wherein the memory functioning member in the memory element includes an electric charge store film extending substantially parallel to a side of the gate electrode.

11. The semiconductor memory device as set forth in claim 1, wherein the semiconductor layer in the memory element has a greater concentration area close to the diffusion area than close to a surface of the semiconductor layer beneath the gate electrode.

12. The semiconductor memory device as set forth in claim 1, wherein:

the memory element has an insulating film separating the channel region or the semiconductor layer from a film having a surface substantially parallel to a surface of the gate insulating film to store electric charge; and

the insulating film is thinner than the gate insulating film and not thicker than 0.8 nm.

13. The semiconductor memory device as set forth in claim 1, wherein each memory functioning member is overlapped with one of the diffusion regions.

14. The semiconductor memory device as set forth in claim 13, wherein an overlap amount of the memory functioning member and the diffusion region is greater than 10 nm.

15. The semiconductor memory device as set forth in claim 1, wherein each diffusion region is disposed so as to be offset from an end of the gate electrode.

16. The semiconductor memory device as set forth in claim 15, wherein a distance between each diffusion region and the end of the gate electrode is less than 100 nm.

17. The semiconductor memory device as set forth in claim 15, wherein the writing or erasing operation to selected one of the memory functioning members provided on both sides of the gate electrode can be executed independently from the other unselected one by controlling each voltage applied to the diffusion region and the gate electrode.

18. A page buffer resource assign method of assigning a page buffer resource in a semiconductor memory device with a memory array of memory elements, the memory elements each including:

a gate electrode provided on a semiconductor layer with an intervening gate insulating film;

a channel region provided beneath the gate electrode;

a diffusion area provided on both sides of the channel region, having an opposite polarity to the channel region; and

a memory functioning member provided on both sides of the gate electrode, having a function of storing electric charge, the memory functioning member being formed by at least one of an insulating film including at least one conductor or semiconductor dot and an insulating film including a ferroelectric film in which inner charge of the ferroelectric film is polarized by an electric filed and in which the polarized state is held;

said method comprising the steps of;

receiving a rewrite page buffer continuous command over a main bus and assigning a first page plane to a user mode so as to enable access to the first page plane over the main bus in the user mode, the first page plane being provided in a page buffer resource connected to the main bus via a first port and to an internal bus via a second port;

receiving a rewrite data block over the main bus and transferring the rewrite data block to the first page plane;

receiving a program containing a page buffer command and assigning the first page plane to a memory control mode so as to enable a memory control circuit to access the first page plane in the memory control mode over the internal bus; and

when a second page plane in the page buffer resource is not assigned to the memory control mode, assigning the second page plane to the user mode.

19. The page buffer resource assign method as set forth in claim 18, further comprising the step of receiving a next rewrite page buffer continuous command and a next rewrite data block over the main bus and transferring the received next rewrite data block to the second page plane.

20. The page buffer resource assign method as set forth in claim 18, further comprising the step of programming the memory array with the rewrite data block from the first page plane while receiving a next rewrite page buffer continuous command and a next rewrite data block over the main bus and transferring the received next rewrite data block to the second page plane.

21. The page buffer resource assign method as set forth in claim 18, wherein the memory functioning member in the memory element includes an electric charge store film extending substantially parallel to a side of the gate electrode.

22. The page buffer resource assign method as set forth in claim 18, wherein the semiconductor layer in the memory element has a greater concentration area close to the diffusion area than close to a surface of the semiconductor layer beneath the gate electrode.

23. The page buffer resource assign method as set forth in claim 18, wherein:

the memory element has an insulating film separating the channel region or the semiconductor layer from a film having a surface substantially parallel to a surface of the gate insulating film to store electric charge; and

the insulating film is thinner than the gate insulating film and not thicker than 0.8 nm.

24. A page buffer resource assign method of assigning a page buffer resource in a semiconductor memory device with a memory array of memory elements, the memory elements each including:

a gate electrode provided on a semiconductor layer with an intervening gate insulating film;

a channel region provided beneath the gate electrode;

a diffusion area provided on both sides of the channel region, having an opposite polarity to the channel region; and

a memory functioning member provided on both sides of the gate electrode, having a function of storing electric charge, the memory functioning member being formed by at least one of an insulating film including at least one conductor or semiconductor dot, and an insulating film including a ferroelectric film in which inner charge of the ferroelectric film is polarized by an electric filed and in which the polarized state is held;

said method comprising the steps of;

the page buffer resource receiving a rewrite page buffer continuous command over a main bus, the page buffer resource including a first page plane and a second page plane and connected to the main bus via a first port and to an internal bus via a second port;

assigning the first page plane to a user mode so as to enable access to the first page plane over the main bus in the user mode;

receiving a rewrite data block over the main bus and transferring the rewrite data block to the first page plane;

receiving a program containing a page buffer command and assigning the first page plane to a memory control mode according to the program so as to enable a memory control circuit to internally access the first page plane in the memory control mode; and

receiving a swap page buffer command over the main bus and swapping the user mode and the memory control mode between the first page plane and the second page plane.

25. The page buffer resource assign method as set forth in claim 24, wherein the memory functioning member in the memory element includes an electric charge store film extending substantially parallel to a side of the gate electrode.

26. The page buffer resource assign method as set forth in claim 24, wherein the semiconductor layer in the memory element has a greater concentration area close to the diffusion area than close to a surface of the semiconductor layer beneath the gate electrode.

27. The page buffer resource assign method as set forth in claim 24, wherein:

the memory element has an insulating film separating the channel region or the semiconductor layer from a film having a surface substantially parallel to a surface of the gate insulating film to store electric charge; and

the insulating film is thinner than the gate insulating film and not thicker than 0.8 nm.

28. A page buffer resource assign circuit assigning a page buffer resource in a semiconductor memory device with a memory array of memory elements, the memory elements each including:

a gate electrode provided on a semiconductor layer with an intervening gate insulating film;

a channel region provided beneath the gate electrode;

a diffusion area provided on both sides of the channel region, having an opposite polarity to the channel region; and

a memory functioning member provided on both sides of the gate electrodes, having a function of storing electric charge, the memory functioning member being formed by at least one of an insulating film including at least one conductor or semiconductor dot, and an insulating film including a ferroelectric film in which inner charge of the ferroelectric film is polarized by an electric filed and in which the polarized state is held;

the page buffer circuit being connected to a main bus via a first port and to an internal bus via a second port;

the page buffer resource assign circuit comprising an assign control circuit;

(1) receiving a rewrite page buffer continuous command over the main bus and assigning a first page plane to a user mode so as to enable access to the first page plane in the page buffer resource over the main bus in the user mode;

(2) receiving a rewrite data block over the main bus and transferring the rewrite data block to the first page plane;

(3) receiving a program containing a page buffer command and assigning the first page plane to a memory control mode according to the program so as to enable a memory control circuit to access the first page plane in the memory control mode over the internal bus; and

(4) when a second page plane in the page buffer resource is not assigned to the memory control mode, assigning the second page plane to the user mode.

29. The page buffer resource assign circuit as set forth in claim 28, further comprising a transfer circuit receiving a next rewrite page buffer continuous command over the main bus, receiving a next rewrite data block over the main bus, and transferring the received next rewrite data block to the second page plane.

30. The page buffer resource assign circuit as set forth in claim 28, further comprising a program circuit programming the memory array with the rewrite data block from the first page plane while receiving a next rewrite page buffer continuous command and a next rewrite data block over the main bus and transferring the received next rewrite data block to the second page plane.

31. The page buffer resource assign circuit as set forth in claim 28, wherein the memory functioning member in the memory element includes an electric charge store film extending substantially parallel to a side of the gate electrode.

32. The page buffer resource assign circuit as set forth in claim 28, wherein the semiconductor layer in the memory element has a greater concentration area close to the diffusion area than close to a surface of the semiconductor layer beneath the gate electrode.

33. The page buffer resource assign circuit as set forth in claim 28, wherein:

the memory element has an insulating film separating the channel region or the semiconductor layer from a film having a surface substantially parallel to a surface of the gate insulating film to store electric charge; and

the insulating film is thinner than the gate insulating film and not thicker than 0.8 nm.

34. A page buffer resource assign circuit assigning a page buffer resource in a semiconductor memory device with a memory array of memory elements, the memory elements each including:

a gate electrode provided on a semiconductor layer with an intervening gate insulating film;

a channel region provided beneath the gate electrode;

a diffusion area provided on both sides of the channel region, having an opposite polarity to the channel region; and

a memory functioning member provided on both sides of the gate electrodes, having a function of storing electric charge, the memory functioning member being formed by at least one of an insulating film including at least one conductor or semiconductor dot, and an insulating film including a ferroelectric film in which inner charge of the ferroelectric film is polarized by an electric filed and in which the polarized state is held;

the page buffer circuit being connected to a main bus via a first port and to an internal bus via a second port;

the page buffer resource assign circuit comprising an assign control circuit;

(1) receiving a rewrite page buffer continuous command over the main bus and assigning a first page plane to a user mode so as to enable access to the first page plane in the page buffer resource over the main bus in the user mode;

(2) receiving a rewrite data block over the main bus and transferring the rewrite data block to the first page plane;

(3) the assign control circuit receiving a program containing a page buffer command and assigning the first page plane to a memory control mode so as to enable a memory control circuit to access the first page plane in the memory control mode over the internal bus; and

(4) receiving a swap page buffer command over the main bus and swapping the user mode and the memory control mode between the first page plane and a second page plane over the main bus according to the according to swap page buffer command.

35. The page buffer resource assign circuit as set forth in claim 34, wherein the memory functioning member in the memory element includes an electric charge store film extending substantially parallel to a side of the gate electrode.

36. The page buffer resource assign circuit as set forth in claim 34, wherein the semiconductor layer in the memory element has a greater concentration area close to the diffusion area than close to a surface of the semiconductor layer beneath the gate electrode.

37. The page buffer resource assign circuit as set forth in claim 34, wherein:

the memory element has an insulating film separating the channel region or the semiconductor layer from a film having a surface substantially parallel to a surface of the gate insulating film to store electric charge; and

the insulating film is thinner than the gate insulating film and not thicker than 0.8 nm.

38. A computer system, comprising:

a central processing unit transferring a command and a rewrite data block over a main bus; and

a semiconductor memory device including a memory array of memory elements and a page buffer resource,

the memory elements each including;

a gate electrode provided on a semiconductor layer with an intervening gate insulating film;

a channel region provided beneath the gate electrode;

a diffusion area provided on both sides of the channel region, having an opposite polarity to the channel region; and

a memory functioning member provided on both sides of the gate electrodes, having a function of storing electric charge, the memory functioning member being formed by at least one of an insulating film including at least one conductor or semiconductor dot, and an insulating film including a ferroelectric film in which inner charge of the ferroelectric film is polarized by an electric filed and in which the polarized state is held,

the page buffer resource being connected to the main bus via a first port and to an internal bus via a second port, wherein;

the semiconductor memory device receives the command over the main bus, assigning the page buffer resource in accordance with the command, and receives and buffers a rewrite data block in the page buffer resource while writing another rewrite data block to the memory array; and

the semiconductor memory device including;

a memory control circuit connected to the internal bus, controlling at least write operation to the memory array; and

an interface circuit connected to the main bus and the page buffer resource, receiving a command over the main bus and generating a control signal to assign page planes in the page buffer resource to a user mode and a memory control mode in accordance with the received command.

39. The computer system as set forth in claim 38, wherein the interface circuit assigns a first one of the page planes to the user mode according to a rewrite page buffer continuous command in the command, receives a rewrite data block over the main bus, and transfers the received rewrite data block to the first page plane.

40. The computer system as set forth in claim 39, wherein the interface circuit, when having received the rewrite page buffer continuous command containing a program including a page buffer command, assigns the first page plane to the memory control mode according to the program.

41. The computer system as set forth in claim 40, wherein the interface circuit, if a second one of the page planes is not assigned to the memory control mode, assigns the second page plane to the user mode, receives a next rewrite page buffer continuous command and a next rewrite data block over the main bus, and transfers the received next rewrite data block to the second page plane.

42. The computer system as set forth in claim 38, wherein:

the page planes include a first page plane and a second page plane; and

the interface circuit assigns the first page plane to the user mode according to a rewrite page buffer continuous command in the command, receives the rewrite data block over the main bus, and transfers the received rewrite data block to the first page plane.

43. The computer system as set forth in claim 42, wherein the interface circuit, when having received the rewrite page buffer continuous command containing a program including a page buffer command, assigns the first page plane to the memory control mode according to the program.

44. The computer system as set forth in claim 43, wherein the interface circuit, if the second page plane is not assigned to the memory control mode, assigns the second page plane to the user mode.

45. The computer system as set forth in claim 38, wherein:

the page planes include a first page plane and a second page plane; and

the interface circuit assigns the second page plane to the user mode according to a rewrite page buffer continuous command in the command, receives the rewrite data block over the main bus, and transfers the received rewrite data block to the second page plane.

46. The computer system as set forth in claim 45, wherein the interface circuit, when having received the rewrite page buffer continuous command containing a program including a page buffer command, assigns the second page plane to the memory control mode according to the program.

47. The computer system as set forth in claim 46, wherein the interface circuit, if the first page plane is not assigned to the memory control mode, assigns the first page plane to the user mode.

48. The computer system as set forth in claim 38, wherein:

the page planes include a first page plane and a second page plane; and

the interface circuit swaps the user mode and the memory control mode between the first page plane and the second page plane according to swap page buffer command in the command.

49. The computer system as set forth in claim 38, wherein the memory functioning member in the memory element includes an electric charge store film extending substantially parallel to a side of the gate electrode.

50. The computer system as set forth in claim 38, wherein the semiconductor layer in the memory element has a greater concentration area close to the diffusion area than close to a surface of the semiconductor layer beneath the gate electrode.

51. The computer system as set forth in claim 38, wherein:

the memory element has an insulating film separating the channel region or the semiconductor layer from a film having a surface substantially parallel to a surface of the gate insulating film to store electric charge; and

the insulating film is thinner than the gate insulating film and not thicker than 0.8 nm.

52. A mobile electronic device, comprising the computer system as set forth in claim 38.

53. A computer system, comprising:

a central processing unit transferring a command and a rewrite data block over a main bus; and

a semiconductor memory device including a memory array of memory elements and a page buffer resource,

the memory elements each including;

a gate electrode provided on a semiconductor layer with an intervening gate insulating film;

a channel region provided beneath the gate electrode;

a diffusion area provided on both sides of the channel region, having an opposite polarity to the channel region; and

a memory functioning member provided on both sides of the gate electrodes, having a function of storing electric charge, the memory functioning member being formed by at least one of an insulating film including at least one conductor or semiconductor dot, and an insulating film including a ferroelectric film in which inner charge of the ferroelectric film is polarized by an electric filed and in which the polarized state is held,

the page buffer resource being connected to the main bus via a first port and to an internal bus via a second port, wherein

the semiconductor memory device includes an assign control circuit;

(1), being connected to the main bus and the second port, receiving a command and assigning the page buffer resource to receive and buffer the rewrite data block while writing another rewrite data block to the memory array;

(2) receiving the rewrite data block over the main bus and transferring the rewrite data block to a first page plane in the page buffer resource;

(3) receiving a rewrite page buffer continuous command over the main bus and assigning the first page plane to a user mode so as to enable access to the first page plane over the main bus in the user mode;

(4) receiving a program including a page buffer command and assigning the first page plane to a memory control mode according to the program so as to enable a memory control circuit to access the first page plane over the internal bus in the memory control mode; and

(5) if a second page plane in the page buffer resource is not assigned to the memory control mode, assigning the second page plane to the user mode.

54. The computer system as set forth in claim 53, wherein the assign control circuit receives a next rewrite page buffer continuous command and a next rewrite data block over the main bus, and transfers the next rewrite data block to the second page plane.

55. The computer system as set forth in claim 53, further comprising a program circuit programming the memory array with the rewrite data block from the first page plane while receiving a next rewrite page buffer continuous command and a next rewrite data block over the main bus and transferring the received next rewrite data block to the second page plane.

56. The computer system as set forth in claim 53, wherein the memory functioning member in the memory element includes an electric charge store film extending substantially parallel to a side of the gate electrode.

57. The computer system as set forth in claim 53, wherein the semiconductor layer in the memory element has a greater concentration area close to the diffusion area than close to a surface of the semiconductor layer beneath the gate electrode.

58. The computer system as set forth in claim 53, wherein:

the memory element has an insulating film separating the channel region or the semiconductor layer from a film having a surface substantially parallel to a surface of the gate insulating film to store electric charge; and

the insulating film is thinner than the gate insulating film and not thicker than 0.8 nm.

59. A mobile electronic device, comprising the computer system as set forth in claim 53.

60. A computer system, comprising:

a central processing unit transferring a command and a rewrite data block over a main bus; and

a semiconductor memory device including a memory array of memory elements and a page buffer resource,

the memory elements each including;

a gate electrode provided on a semiconductor layer with an intervening gate insulating film;

a channel region provided beneath the gate electrode;

a diffusion area provided on both sides of the channel region, having an opposite polarity to the channel region; and

a memory functioning member provided on both sides of the gate electrodes, having a function of storing electric charge, the memory functioning member being formed by at least one of an insulating film including at least one conductor or semiconductor dot, and an insulating film including a ferroelectric film in which inner charge of the ferroelectric film is polarized by an electric filed and in which the polarized state is held, the page buffer resource being connected to the main bus via a first port and to an internal bus via a second port, having a first page plane and a second page plane, wherein

the semiconductor memory device includes an assign control circuit;

(1), being connected to the main bus and the second port, receiving a command and assigning the page buffer resource to receive and buffer the rewrite data block while writing another rewrite data block to the memory array;

(2) receiving a rewrite page buffer continuous command over the main bus and assigning the first page plane to a user mode so as to enable access to the first page plane in the page buffer resource over the main bus in the user mode;

(3) receiving the rewrite data block over the main bus and transferring the rewrite data block to the first page plane;

(4) receiving a program including page buffer command and assigning the first page plane to a memory control mode according to the program.

61. The computer system as set forth in claim 60, wherein the memory functioning member in the memory element includes an electric charge store film extending substantially parallel to a side of the gate electrode.

62. The computer system as set forth in claim 60, wherein the semiconductor layer in the memory element has a greater concentration area close to the diffusion area than close to a surface of the semiconductor layer beneath the gate electrode.

63. The computer system as set forth in claim 60, wherein:

the memory element has an insulating film separating the channel region or the semiconductor layer from a film having a surface substantially parallel to a surface of the gate insulating film to store electric charge; and

the insulating film is thinner than the gate insulating film and not thicker than 0.8 nm.

64. A mobile electronic device, comprising the computer system as set forth in claim 60.