Nonvolatile memory system, semiconductor memory, and writing method

• US 7,405,979 B2
• Filed: 09/07/2007
• Issued: 07/29/2008
• Est. Priority Date: 07/09/1996
• Status: Expired due to Fees

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: Renesas Technology Corporation (Renesas Electronics Corporation)
• Inventors: Ishii, Tatsuya, Tsuchiya, Osamu, Miwa, Hitoshi, Kubono, Shooji
• Primary Examiner(s): Elms; Richard T.
• Assistant Examiner(s): Nguyen; Hien N
• Application Number:
  US11/896,969
• Publication Number:
  US 20080008009A1
• Time in Patent Office: 326 Days
• Field of Search: 365/185.18, 365/185.02, 365/185.24, 365/185.29, 365/185.3, 365/185.23
• US Class Current: 365/185.29
• CPC Class Codes: G11C 16/0491 Virtual ground arrays
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 16/12 Programming voltage switching circuits
• CPC Class Codes: G11C 16/16 for erasing blocks, e.g. arrays, words, groups
• CPC Class Codes: G11C 16/3404 Convergence or correction of memory cell threshold voltages; Repair or recovery of overerased or overprogrammed cells
• CPC Class Codes: G11C 16/3427 Circuits or methods to prevent or reduce disturbance of the state of a memory cell when neighbouring cells are read or written
• CPC Class Codes: G11C 16/3431 Circuits or methods to detect disturbed nonvolatile memory cells, e.g. which still read as programmed but with threshold less than the program verify threshold or read as erased but with threshold greater than the erase verify threshold, and to reverse the disturbance via a refreshing programming or erasing step
• CPC Class Codes: G11C 16/3459 Circuits or methods to verify correct programming of nonvolatile memory cells
• CPC Class Codes: G11C 2216/18 Flash erasure of all the cells in an array, sector or block simultaneously

Abstract

A nonvolatile semiconductor memory recovers variation in the threshold of a memory cell due to disturbance related to a word line. The nonvolatile memory continuously performs many writing operations without carrying out single-sector erasing after each writing operation, performing the additional writing operations quicker than the usual writing operation, and lightening the burden imposed on software for use in additional writing. The data stored in a designated sector is read out before being saved in a register, and the selected sector is subjected to single-sector erasing when a predetermined command is given. Then write expected value data is formed from the saved data and data to be additionally written, completing the writing operation.

Claims

1. A method of programming for a nonvolatile memory, which comprises a plurality of word lines, each of which is coupled with memory cells, and is adapted to perform an erase operation and a program operation,

wherein in the erase operation, plural memory cells coupled to a selected word line move into an erase state by supplying a first voltage,

wherein in the program operation, a first plurality of said memory cells coupled to the selected word line are in the erase state and a second plurality of said memory cells coupled to the selected word line are in a corresponding state in accordance with first data before performing the program operation, wherein the method comprises the steps of:

inputting second data to be programmed to the first plurality of memory cells coupled to the selected word line,

supplying the erase voltage to plural memory cells coupled to the selected word line, and

programming the second data to the first plurality of memory cells coupled to the selected word line, the second plurality of memory cells coupled to the selected word line remaining in the corresponding state in accordance with the first data before performing the program operation,

wherein the time of supplying the erase voltage in the program operation is shorter than the time of supplying the erase voltage in the erase operation.

2. A method of programming for the nonvolatile memory according to claim 1,

wherein the first data already programmed to the second plurality of memory cells before performing the program operation is management information.

3. A method of programming for the nonvolatile memory according to claim 2,

wherein a data length of the second data is 512 bytes, and

wherein the memory cells coupled to the selected word line are capable of being programmed with data more than 512 bytes.

4. A method of programming for the nonvolatile memory according to claim 1,

wherein each of the memory cells coupled to the selected word line has a threshold voltage within one of an erase state voltage range and a program state voltage range, and

wherein the threshold voltage of the first plurality of memory cells between supplying the erase voltage and programming the second data is an intermediate voltage between the erase state voltage range and the program state voltage range.