Pseudo-noise correlator for GPS spread-spectrum receiver

• US 7,406,114 B2
• Filed: 11/24/2003
• Issued: 07/29/2008
• Est. Priority Date: 04/25/1996
• Status: Expired due to Fees

• Current Assignee: CSR Technology Incorporated (Qualcomm, Inc.)
• Original Assignee: SIRF Technology Incorporated (Qualcomm, Inc.)
• Inventors: Kohli, Sanjai, Cahn, Charles R., Chansarkar, Mangesh, Chen, Steven, Turetsky, Greg
• Primary Examiner(s): WANG, TED M
• Application Number:
  US10/722,694
• Publication Number:
  US 20040136446A1
• Time in Patent Office: 1,709 Days
• Field of Search: 375/150, 375/130, 375/134, 375/137, 375/142, 375/147, 342/352, 342/357.12, 701/251, 701/205, 701/213, 701/215, 702/343
• US Class Current: 375/150
• CPC Class Codes: G01C 21/26 specially adapted for navigation in a road network
• CPC Class Codes: G01C 22/00 Measuring distance traversed on the ground by vehicles, persons, animals or other moving solid bodies, e.g. using odometers, using pedometers
• CPC Class Codes: G01S 19/11 wherein the cooperating elements are pseudolites or satellite radio beacon positioning system signal repeaters
• CPC Class Codes: G01S 19/22 Multipath-related issues
• CPC Class Codes: G01S 19/235 Calibration of receiver components
• CPC Class Codes: G01S 19/29 carrier including Doppler, related G01S19/246 takes precedence
• CPC Class Codes: G01S 19/30 code related G01S19/246 takes precedence
• CPC Class Codes: G01S 19/34 Power consumption
• CPC Class Codes: G01S 19/37 Hardware or software details of the signal processing chain
• CPC Class Codes: G01S 19/47 the supplementary measurement being an inertial measurement, e.g. tightly coupled inertial
• CPC Class Codes: G01S 19/49 whereby the further system is an inertial position system, e.g. loosely-coupled
• CPC Class Codes: G01S 19/50 whereby the position solution is constrained to lie upon a particular curve or surface, e.g. for locomotives on railway tracks
• CPC Class Codes: H04B 1/707 using direct sequence modulation
• CPC Class Codes: H04B 1/7085 using a code tracking loop, e.g. a delay-locked loop
• CPC Class Codes: H04B 1/709 Correlator structure
• CPC Class Codes: H04B 1/7095 Sliding correlator type
• CPC Class Codes: H04B 1/7115 Constructive combining of multi-path signals, i.e. RAKE receivers
• CPC Class Codes: H04B 2001/70706 using a code tracking loop, e.g. a delay locked loop
• CPC Class Codes: H04B 2201/70715 with application-specific features
• CPC Class Codes: H04B 7/216 Code division or spread-spectrum multiple access [CDMA, SSMA]
• CPC Class Codes: H04L 27/30 : wherein each code element is represented by a combination of frequencies

Abstract

A terrestrial C/A code GPS receiver system digitally samples, filters and stores a segment of 11 half chips of the received composite as a binary number and multiplexes this number for parallel correlation with each of a series of multibit code replicas for the satellites to be tracked. Each of the time delay specific correlation products are accumulated in a cell of a memory matrix so that at least twenty two delays for each satellite may be evaluated each code period providing fast reacquisition, even within a city intersection, as well as correction of multipath tracking and multipath interference. All cells of the memory matrix may be used for an acquisition of a single satellite in about 4 ms. Two satellite tracking, in addition to altitude hold, uses cross track hold alternating with clock hold to update the cross track estimate. Single satellite tracking uses cross track and clock hold together. Navigation data is updated with detected changes in motion including turns.

Claims

1. A system for operating a GPS coarse acquisition (C/A) code receiver comprising:

a plurality of channel means, each comprising;

means for forming x multibit digital segment values per C/A code period, x being an integer, each multibit digital segment value representing a sequential code segment of a received composite of satellite signals; and

a plurality of correlating meats for correlating each multibit digital segment value with n satellite specific sets of m different time delayed segments of C/A code, n and m being integers, to form at least n times m delay specific correlation values, wherein m is greater than the number of bits in each multibit digital segment value.

2. A system as in claim 1, further comprising a quadrature signal separator, the quadrature signal separator representing each digital segment value as a pair of quadrature signals.

3. A system as in claim 2, further comprising:

a numerically controlled oscillator;

a multiplier;

a sine and cosine table accessed by the numerically controlled oscillator to provide rotational values for each pair of quadrature signals, the rotational values being multiplied with the quadrature signals in the multiplier and the product thereof being provided to the correlators for computing the correlation values.

4. A system as in claim 1, wherein each pair of time delayed segments within each set of time delayed segments are separated from each other by a multiple of half-chip separations.

5. A system as in claim 1, wherein each pair of time delayed segments within each set of time delayed segments are separated from each other by a multiple of quarter-chip separations.

6. A system as in claim 1, wherein the number of bits in each multibit digital segment value is one or more times a value selected from the prime factors of then number of chips in a C/A code.

7. A system as in claim 6, wherein the number of bits in each multibit digital segment value is 11.

8. A system as in claim 1, wherein m is one or more times a value selected from the prime factors of then number of chips in a C/A code.

9. A system as in claim 1, wherein m is greater than or equal to 22.

10. A system as in claim 1, wherein n is one or more times a value selected from the prime factors of then number of chips in a C/A code.

11. A system as in claim 1, wherein n is greater than or equal to 12.

12. A system as in claim 1, wherein the product of m, n and the bits in each multibit digital segment value is one or more times the number of chips in a C/A code.