Very high data rate up-conversion in FPGAs

• US 7,406,134 B1
• Filed: 03/04/2004
• Issued: 07/29/2008
• Est. Priority Date: 03/04/2004
• Status: Expired due to Fees

• Current Assignee: Altera Corporation (Intel Corporation)
• Original Assignee: Altera Corporation (Intel Corporation)
• Inventors: Esposito, Ben
• Primary Examiner(s): Ahn; Sam K
• Application Number:
  US10/795,189
• Time in Patent Office: 1,608 Days
• Field of Search: 375/260, 375/269, 375/273, 375/279, 375/280, 375/281, 375/282, 375/283, 375/295, 375/308, 332/103, 332/104, 332/105, 327/233, 327/238, 327/254
• US Class Current: 375/308
• CPC Class Codes: H03D 7/166 using two or more quadrature frequency translation stages

Abstract

Methods, circuits, and apparatus for providing an RF up-converter using digital circuits. One exemplary embodiment provides an up-converter that uses multiple channels of parallel digital processing, then serializes individual bits from these channels to achieve higher frequencies. Specifically, I and Q components of a signal to be transmitted are decomposed into multiple components, each phase shifted from another. Quadrature versions of an oscillator signal are similarly decomposed and multiplied with corresponding I and Q signal components. The products are combined and serialized on a bit-by-bit basis to generate an RF signal.

Claims

1. An integrated circuit comprising:

an up-converter comprising;

a first filter having N outputs, where each output provides a signal shifted in phase from one another;

a second filter having N outputs, where each output provides a signal shifted in phase from one another;

an oscillator providing 2 times N outputs, where the 2 times N outputs provide N pairs of quadrature signals and where each pair of the quadrature signals are shifted in phase from one another;

a first plurality of mixers, each mixer receiving one of the N outputs from the first filter and one of the 2 times N outputs from the oscillator;

a second plurality of mixers, each mixer receiving one of the N outputs from the second filter and one of the 2 times N outputs from the oscillator, wherein an output of each of the first plurality of mixers is combined with an output of the second plurality of mixers; and

a plurality of parallel-to-serial converters, each parallel-to-serial converter receiving a bit from each of the combined outputs of the mixers and providing a serial output.

2. The integrated circuit of claim 1 wherein each parallel-to-serial converter comprises a plurality of registers coupled as a shift register.

3. The integrated circuit of claim 1 wherein each parallel-to-serial converter comprises a serializer.

4. The integrated circuit of claim 1 wherein the plurality of parallel-to-serial converters are coupled to a digital-to-analog converter.

5. The integrated circuit of claim 1 wherein the oscillator is a numerically controlled oscillator.

6. The integrated circuit of claim 5 wherein the numerically controlled oscillator comprises a plurality of lookup tables, each lookup table comprising a plurality of entries.

7. The integrated circuit of claim 1 wherein the first filter and the second filter are each a multi-tap finite-impulse-response filter.

8. A method of up-converting a signal comprising:

receiving in-phase and quadrature versions of a signal;

decomposing the in-phase version of the signal into a first plurality of signals, each phase shifted from each other;

decomposing the quadrature version of the signal into a second plurality of signals, each phase shifted from each other;

multiplying each of the first plurality of signals with a corresponding one of a third plurality of signals to generate a fourth plurality of signals;

multiplying each of the second plurality of signals with a corresponding of a fifth plurality of signals to generate a sixth plurality of signals;

adding each of the fourth plurality of signals with a corresponding one of the sixth plurality of signals to generate a seventh plurality of signals;

serializing a plurality of most significant bits of the seventh plurality of signals to generate an eighth signal; and

serializing a plurality of least significant bits of the seventh plurality of signals to generate a ninth signal.

9. The method of claim 8 wherein the serializing of the plurality of most significant bits of the seventh plurality of signals is done by a serializer circuit.

10. The method of claim 9 wherein the serializer circuit comprises a plurality of registers configured as a shift register.

11. The method of claim 9 wherein the third and fifth plurality of signals are generated by a numerically controlled oscillator.

12. The method of claim 11 wherein the numerically controlled oscillator comprises a plurality of lookup tables.

13. The method of claim 9 wherein each of the third plurality of signals is approximately in quadrature with one of the fifth plurality of signals.

14. The method of claim 8 further comprising:

converting the eighth signal to an analog signal;

filtering the analog signal; and

applying the filtered analog signal to an antenna.

15. The method of claim 8 further comprising:

serializing a plurality of intermediate bits of the seventh plurality of signals to generate a tenth signal.

16. An integrated circuit including an up-converter comprising:

a first polyphase filter having a first plurality of outputs providing a first plurality of output signals, where each of the first plurality of output signals are shifted in phase from one another;

a second polyphase filter having a second plurality of outputs providing a second plurality of output signals, where each of the second plurality of output signals are shifted in phase from one another;

an oscillator having a third plurality of outputs providing a third plurality of output signals, where each of the third plurality of output signals are shifted in phase from one another, the oscillator further having a fourth plurality of outputs providing a fourth plurality of output signals, where each of the fourth plurality of output signals are shifted in phase from one another, and where each of the fourth plurality of output signals are in quadrature with a corresponding one of the third plurality of output signals;

a first plurality of mixers, each of the first plurality of mixers coupled to one of the first plurality of outputs from the first polyphase filter and one of the third plurality of outputs from the oscillator;

a second plurality of mixers, each of the second plurality of mixers coupled to one of the second plurality of outputs from the second polyphase filter and one of the fourth plurality of outputs from the oscillator;

a plurality of adders, each coupled to an output of one of the first plurality of mixers and an output from one of the second plurality of mixers; and

a plurality of parallel-to-serial converters, each parallel-to-serial converter coupled to an output of each of the plurality of adders.

17. The integrated circuit of claim 16 wherein the parallel-to-serial converter comprises a plurality of registers coupled as a shift register.

18. The integrated circuit of claim 16 wherein the plurality of parallel-to-serial converters are coupled to a digital-to-analog converter.

19. The integrated circuit of claim 16 wherein the oscillator is a numerically controlled oscillator.

20. The integrated circuit of claim 19 wherein the numerically controlled oscillator comprises a plurality of lookup tables, each lookup table comprising a plurality of entries.

21. The integrated circuit of claim 16 wherein the first polyphase filter and the second polyphase filter each comprise a multi-tap finite-impulse-response filter.