Universal memory circuit architecture supporting multiple memory interface options

• US 7,406,572 B1
• Filed: 03/01/2005
• Issued: 07/29/2008
• Est. Priority Date: 03/26/2004
• Status: Expired due to Fees

• Current Assignee: Cypress Semiconductor Corporation (Infineon Technologies AG)
• Original Assignee: Cypress Semiconductor Corporation (Infineon Technologies AG)
• Inventors: Nguyen, Simon B.
• Primary Examiner(s): Ellis, Kevin L.
• Assistant Examiner(s): Lo, Kenneth M
• Application Number:
  US11/069,499
• Time in Patent Office: 1,246 Days
• Field of Search: 711/107, 711/101, 711/167, 711/202, 711/154
• US Class Current: 711/154
• CPC Class Codes: G06F 13/1694 Configuration of memory controller to different memory types
• CPC Class Codes: G11C 7/10 Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
• CPC Class Codes: G11C 7/1045 Read-write mode select circuits

Abstract

An architecture for an improved non-volatile memory device supporting multiple memory interface options is disclosed herein. In one embodiment, the improved memory device includes a magnetic random access memory (MRAM) array and at least one memory interface block, which is configured for accessing a different type of memory array other than the MRAM array. A smart MRAM interface block is also included and coupled between the plurality of memory interface blocks and the MRAM array. The smart MRAM array is configured for accessing the MRAM array using commands intended for the MRAM array, as well as commands intended for the different type of memory array. A method for operating the improved non-volatile memory device is also disclosed herein.

Claims

1. A memory circuit architecture, comprising:

a magnetic random access memory (MRAM) array; and

a plurality of memory interface blocks, each configured for accessing a different type of memory array, wherein one of the plurality of memory interface blocks is configured for;

using a first set of commands received by the memory circuit architecture to access the MRAM array; and

translating a second set of commands received by the memory circuit architecture into a format recognized by the MRAM array and using the translated commands to access the MRAM array.

2. The memory circuit architecture of claim 1, wherein the plurality of memory interface blocks comprise one or more interface blocks selected from a group consisting of:

a NAND Flash interface, a NOR Flash interface, a Compact Flash (CF) interface, and various types of Random Access Memory (RAM) and Read Only Memory (ROM) interfaces.

3. The memory circuit architecture of claim 2, wherein the plurality of memory interface blocks comprise a NAND Flash interface, a NOR Flash interface, and a Compact Flash (CF) interface.

4. The memory circuit architecture of claim 3, wherein the one of the plurality of memory interface blocks comprises a Magnetic Random Access Memory (MRAM) interface coupled for receiving the first set of commands, which are intended for accessing the MRAM array, as well as the second set of commands, which were initially intended for accessing a different type of memory array.

5. The memory circuit architecture of claim 4, further comprising:

an input/output (I/O) block coupled for receiving the first set of commands or the second sets of commands from an external source; and

a configuration block configured for selectively activating at least one of the plurality of memory interface blocks for accessing the MRAM array.

6. The memory circuit architecture of claim 5, wherein the configuration block is configured for activating the at least one of the plurality of memory interface blocks via hardwired or programmable means.

7. The memory circuit architecture of claim 6, wherein the programmable means comprise software-implemented logic or programmable fuses.

8. The memory circuit architecture of claim 6, wherein the configuration block is configured for activating the MRAM interface and deactivating all other interface blocks during times in which the first set of commands are received by the memory circuit architecture.

9. The memory circuit architecture of claim 6, wherein the configuration block is configured for activating another memory interface along with the MRAM interface, and deactivating all other interface blocks, during times in which the second set of commands are received by the memory circuit architecture.

10. The memory circuit architecture of claim 9, wherein the MRAM interface comprises logic, in the form of hardware and/or software, for translating the second set of commands into the format recognized by the MRAM array.

11. The memory circuit architecture of claim 10, wherein the MRAM interface enables the memory circuit architecture to emulate different types of memory arrays, while utilizing desired features of the MRAM array.

12. The memory circuit architecture of claim 11, wherein the desired features comprise less complex programming, faster and more reliable read/write operations, and decreased power consumption, as compared to conventional Flash memory arrays.

13. A memory product, comprising:

a magnetic random access memory (MRAM) array;

at least one memory interface block configured for accessing a different type of memory array other than the MRAM array, wherein the at least one memory interface block is selected from a group consisting of;

a NAND Flash interface, a NOR Flash interface, a Compact Flash (CF) interface, and various types of Random Access Memory (RAM) and Read Only Memory (ROM) interfaces; and

a MRAM interface block coupled between the at least one memory interface block and the MRAM array, wherein the MRAM interface block is configured for accessing the MRAM array using commands intended for the MRAM array, as well as commands intended for the different type of memory array.

14. The memory product of claim 13, wherein the MRAM array, the at least one memory interface block and the MRAM interface block are all incorporated within a single package, which can be used to replace other memory products previously existing within a system without making any hardware/software changes to the system layout or operation.

15. A method for operating a memory circuit including a magnetic random access memory (MRAM) array, the method comprising:

receiving a first set of commands corresponding to one of a plurality of memory interface blocks included within the memory circuit for accessing the MRAM array; and

translating a second set of commands into a format recognized by the MRAM array and using the translated commands to access the MRAM array, if the second set of commands are initially formatted for accessing a type of memory array other than the MRAM array.

16. The method of claim 15, further comprising using the first set of commands to access the MRAM, if the received commands are initially formatted for accessing the MRAM array.

17. The method of claim 16, wherein the plurality of memory interface blocks comprise two or more interface blocks selected from a group consisting of:

a MRAM interface, a NAND Flash interface, a NOR Flash interface, a Compact Flash (CF) interface, and various types of Random Access Memory (RAM) and Read Only Memory (ROM) interfaces.

18. The method of claim 17, further comprising selecting at least one of the plurality of memory interface blocks to be used for accessing the MRAM array.

19. The method of claim 18, wherein the step of selecting is a static process performed only once before the step of receiving.

20. The method of claim 18, wherein the step of selecting is a manual process performed one or more times by a user of the memory circuit.

21. The method of claim 18, wherein the step of selecting is a dynamic process dependent on a particular format of the received commands.

22. The method of claim 18, further comprising receiving a command sequencing signal along with the received commands to determine an operational mode of the memory circuit.

23. The method of claim 22, further comprising using the command sequencing signal to select the operational mode from a plurality of operational modes comprising a device selection mode, a reduced pin count mode and an extended addressing mode.

24. The method of claim 22, further comprising using the command sequencing signal to obtain status and identification information from a storage element arranged within the memory circuit.

25. The method of claim 22, further comprising using command sequencing signal to supply commands associated with a selected memory interface block to a command processing unit arranged within the memory circuit.