Control unit for generating a clock pulse as a function of output signals outputted from at least two clock outputs

• US 7,406,615 B2
• Filed: 07/22/2004
• Issued: 07/29/2008
• Est. Priority Date: 10/13/2003
• Status: Active Grant

• Current Assignee: Robert Bosch GmbH
• Original Assignee: Robert Bosch GmbH
• Inventors: Malicki, Siegfried, Mattes, Bernhard
• Primary Examiner(s): SURYAWANSHI, SURESH
• Application Number:
  US10/576,221
• Publication Number:
  US 20070277054A1
• Time in Patent Office: 1,468 Days
• Field of Search: 713/400, 713/500, 713/503
• US Class Current: 713/500
• CPC Class Codes: G06F 11/1604 where the fault affects the clock signals of a processing unit and the redundancy is at or within the level of clock signal generation hardware
• CPC Class Codes: G06F 11/1608 Error detection by comparing the output signals of redundant hardware G06F11/1629, G06F11/1666 take precedence; error detection or correction in information storage based on relative movement between record carrier and transducer G11B20/18; checking static stores for correct operation G11C29/00; for logic circuits H03K19/003, H03K19/007; for pulse counters or frequency dividers H03K21/40
• CPC Class Codes: H03K 5/19 Monitoring patterns of pulse trains indicating amplitude G01R19/00; indicating frequency G01R23/00; measuring characteristics of individual pulses G01R29/02

Abstract

A control unit featuring clocked data transmission between a processor and at least one further circuit, the processor itself outputting the clock pulse. The processor monitors the clock pulse based on the output signals of at least two clock outputs.

Claims

1. A control unit comprising:

a processor outputting a clock pulse;

at least one further circuit, wherein;

a clocked data transmission occurs between the processor and the at least one further circuit;

the processor monitors the clock pulse based on output signals of at least two clock outputs; and

the at least two clock outputs are connected in such a manner that the clock pulse is generated as a function of the output signals; and

an OR element to which the at least two clock outputs are supplied to generate the clock pulse.

2. The control unit as recited in claim 1, wherein:

the OR element comprises;

a first diode; and

a second diode; and

the first diode and the second diode cooperate to perform an OR operation on the at least two clock outputs.

3. The control unit as recited in claim 1, wherein the clock pulse is supplied to at least one of an impedance transformer and an amplifier.

4. The control unit as recited in claim 1, wherein the at least two clock outputs are assigned to different port groups.

5. The control unit as recited in claim 1, wherein the at least two clock outputs are connected in such a manner that the control unit generates a monitoring signal as a function of the output signals.

6. The control unit as recited in claim 5, further comprising:

an exclusive-OR element to which the output signals are supplied, respectively, wherein the monitoring signal is generated as a function of a signal of the exclusive-OR element.

7. The control unit as recited in claim 1, wherein:

the at least two clock outputs are connected in such a manner that the output signals are fed back respectively to a first input and a second input of the processor in order for the processor to monitor the output signals and to generate a monitoring signal as a function thereof.

8. The control unit as recited in claim 7, wherein the first input and the second input are assigned to different port groups.