Systems and methods for forward error correction in a wireless communication network

• US 7,406,647 B2
• Filed: 09/27/2004
• Issued: 07/29/2008
• Est. Priority Date: 12/06/2001
• Status: Expired due to Term

• Current Assignee: Intellectual Ventures Holding 81 LLC (Intellectual Ventures LLC)
• Original Assignee: Pulse-Link Incorporated
• Inventors: Lakkis, Ismail
• Primary Examiner(s): Chaudry, M. Mujtaba K
• Application Number:
  US10/952,485
• Publication Number:
  US 20050201315A1
• Time in Patent Office: 1,401 Days
• Field of Search: 714/800, 714/758, 375/240.07
• US Class Current: 714/758
• CPC Class Codes: H04B 1/7163 using impulse radio
• CPC Class Codes: H04B 1/71635 Transmitter aspects H04B1/7174 takes precedence
• CPC Class Codes: H04B 1/719 Interference-related aspects
• CPC Class Codes: H04B 2201/709709 Methods of preventing interference
• CPC Class Codes: H04L 1/0006 by adapting the transmission format
• CPC Class Codes: H04L 1/0026 Transmission of channel quality indication
• CPC Class Codes: H04L 1/0041 Arrangements at the transmitter end
• CPC Class Codes: H04L 1/0057 Block codes H04L1/0061, H04L1/0064 take precedence
• CPC Class Codes: H04L 7/041 using special codes as synchronising signal

Abstract

A forward error correction encoder encodes input data words into code words that comprise a parity matrix. In one aspect, the encoder is optimized based on the properties of the parity matrix in order to reduce routing overhead size.

Claims

1. An FEC encoder, comprising:

a plurality of block cyclic shift registers;

a plurality of fixed connections between each of the plurality of block cyclic shift registers; and

a plurality of XOR gates coupled to the plurality of fixed connections, the fixed connections fixed such that the first fixed connection between each of the plurality of block cyclic shift registers is coupled to the first of the plurality of XOR gates, the second fixed connection between each of the plurality of block cyclic shift registers is connected to the second of the plurality of XOR gates, and so on until the last of the fixed connections between each of the block cyclic shift registers is coupled to the last of the plurality of XOR gates.

2. The FEC encoder of claim 1, further comprising a register configured to store the output of each of the plurality of XOR gates.

3. The FEC encoder of claim 2, further comprising another XOR gate coupled to the output of the register, the other XOR gate configured to XOR the output of the register with a delayed version of the output of the register.

4. The FEC encoder of claim 1, wherein the FEC encoder is configured to produce a code word from input data bits.

5. The FEC encoder of claim 4, wherein the code word is generated using a parity matrix.

6. The FEC encoder of claim 5, wherein the parity matrix comprises a dual diagonal matrix.

7. The FEC encoder of claim 6, wherein the parity matrix comprises a matrix of block cyclic matrices.

8. The FEC encoder of claim 7, wherein the plurality of fixed connections are fixed, based on the dual diagonal matrix and the matrix of block cyclic matrices.

9. The FEC encoder of claim 7, wherein each of the plurality of block cyclic matrices are generated from an identity matrix and a permutation vector.

10. The FEC encoder of claim 9, wherein the first of the plurality of block cyclic matrices is generated directly from the identity matrix and a permutation vector, and each of the subsequent block cyclic matrices are generated by rotating the previous block cyclic matrix.

11. A wireless transmitter, comprising:

a processor configured to generate data to be transmitted by the transmitter, and

an FEC encoder configured to generate a code word based on the data, the FEC encoder comprising;

a plurality of block cyclic shift registers configured to receive the data and shift it through the plurality of block cyclic shift registers;

a plurality of fixed connections between each of the plurality of block cyclic shift registers configured to allow the data to be shifted through the plurality of block cyclic shift registers; and

a plurality of XOR gates coupled to the plurality of fixed connections, the fixed connections fixed such that the first fixed connection between each of the plurality of block cyclic shift registers is coupled to the first of the plurality of XOR gates, the second fixed connection between each of the plurality of block cyclic shift registers is connected to the second of the plurality of XOR gates, and so on until the last of the fixed connections between each of the block cyclic shift registers is coupled to the last of the plurality of XOR gates.

12. The transmitter of claim 11, further comprising a register configured to store the output of each of the plurality of XOR gates.

13. The transmitter of claim 12, further comprising another XOR gate coupled to the output of the register, the other XOR gate configured to XOR the output of the register with a delayed version of the output of the register.

14. The transmitter of claim 11, wherein the code word is generated using a parity matrix.

15. The transmitter of claim 14, wherein the parity matrix comprises a dual diagonal matrix.

16. The transmitter of claim 15, wherein the parity matrix comprises a matrix of block cyclic matrices.

17. The transmitter of claim 16, wherein the plurality of fixed connections are fixed based on the dual diagonal matrix and the matrix of block cyclic matrices.

18. The transmitter of claim 16, wherein each of the plurality of block cyclic matrices are generated from an identity matrix and a permutation vector.

19. The transmitter of claim 18, wherein the first of the plurality of block cyclic matrices is generated directly from the identity matrix and a permutation vector, and each of the subsequent block cyclic matrices are generated by rotating the previous block cyclic matrix.