Semiconductor memory device and signal processing system

• US 7,406,649 B2
• Filed: 05/26/2005
• Issued: 07/29/2008
• Est. Priority Date: 05/31/2004
• Status: Active Grant

• Current Assignee: Tessera Advanced Technologies Inc (Adeia Inc.)
• Original Assignee: Sony Corporation (Sony Group Corp.)
• Inventors: Itoh, Masahiko, Shimizume, Kazutoshi, Akita, Mamoru
• Primary Examiner(s): Torres; Joseph D
• Application Number:
  US11/137,442
• Publication Number:
  US 20050268208A1
• Time in Patent Office: 1,160 Days
• Field of Search: 714/755, 714/763, 714/773
• US Class Current: 714/773
• CPC Class Codes: G06F 11/1068 in sector programmable memories, e.g. flash disk G06F11/1072 takes precedence

Abstract

The disclosed semiconductor memory device exhibits improved error correction capability shorter read/write times, and removes or reduces the need for redundant memory The semiconductor device has a data input portion for receiving one page of data, dividing it to a plurality of code words, generating and adding check code (parity data) for each code word, successively forming main code words, and transferring the main code words to one of a plurality of memory banks. The semiconductor device also includes a data output portion for receiving one page worth of data, including main code words transferred from the data latch circuit, correcting errors in the data when the data includes fewer than a predetermined number of errors for each main code word, adding the error information to each read code word, and outputting the result.

Claims

1. A semiconductor memory device, comprising:

a cell array formed by a plurality of memory cells arranged in a matrix and into which page data including a plurality of main code words is written in units of a plurality of memory cells,

a latch circuit for latching the page data to be written including at least the plurality of main code words,

a data input portion for dividing the page data to be written into a plurality of code words, checking each code word and generating check codes, adding the check codes to corresponding code words to form main code words, and successively transferring the formed main code words to the latch circuit, and

a control circuit for writing the page data into the cell array all together when the page data including a plurality of main code words added with the check codes are latched by the latch circuit.

2. A semiconductor memory device as set forth in claim 1, wherein the data input portion includes:

a latch circuit for latching the page data to be written including at least the plurality of main code words,

a plurality of shift registers able to successively shift and hold the code words included in the page data to be written,

a first switch circuit for receiving the page data to be written including code words able to be divided into a plurality of code words and inputting at least successive code words to the different shift registers,

a second switch circuit for selectively outputting the code word data of each shift register in which the code words are all shifted,

a check code generation circuit for checking the code words selected so as to be output by the second switch circuit and generating the check codes, and

an additional circuit for adding the check codes to the code words selectively output by the second switch circuit and outputting the same as the main code words to the latch circuit.

3. A semiconductor memory device as set forth in claim 1, wherein said cell array formed by memory cells arranged in a matrix includes NAND memory strings formed by a plurality of memory cells connected in series.

4. A semiconductor memory device as set forth in claim 1, wherein the units of pages are units of word lines.

5. A semiconductor memory device, comprising:

a cell array formed by a plurality of memory cells arranged in the matrix and in which page data, including a plurality of main code words having check codes, are recorded,

a latch circuit that latches the page data read out from the cell array,

a data output portion comprising

an input that receives the page data transferred from the latch circuit,

a plurality of shift registers, arranged in parallel, that successively shift and hold the code words, except the check codes, from the page data transferred from the latch circuit, wherein the plurality of main code words from the page data are alternately input to different shift registers among the plurality of shift registers,

a first switch circuit for receiving the read out page data and inputting successive code words to different shift registers from the plurality of shift registers,

a second switch circuit for selectively outputting the code word data from each shift register from the plurality of shift registers,

a correction circuit, positioned in parallel with the plurality of shift registers, that corrects errors in the page data when the number of errors in a given main code word is within a predetermined number of errors, adding corresponding error correction information to the given code word, except the check code, and outputting the result,

a control circuit for reading the page data from the cell array and making the latch circuit latch the page data and transfer the latch data to the data output portion.

6. A semiconductor memory device as set forth in claim 5, wherein the data output further comprises:

an additional circuit that adds the error correction information from the error correction circuit to the code words output by the second switch circuit and outputting corrected code words.

7. A semiconductor memory device as set forth in claim 6, wherein said data output portion further comprises a syndrome data generator, and syndrome data output, and wherein while performing error correction, the error correction circuit outputs the syndrome data when it is unable to correct an error.

8. A semiconductor memory device as set forth in claim 7, wherein the error correction circuit of said data output portion further comprises an output for indicating the state of the error correction.

9. A semiconductor memory device as set forth in claim 5, wherein the data output portion further comprises a syndrome data generator and a syndrome data output, and wherein the data output portion outputs the syndrome data when it is unable to correct the error while performing the error correction.

10. A semiconductor memory device as set forth in claim 9, wherein the data output portion further comprises an output for indicating the state of the error correction.

11. A semiconductor memory device as set forth in claim 5, wherein said cell array formed by memory cells arranged in a matrix includes NAND memory strings formed by a plurality of memory cells connected in series.

12. A semiconductor memory device as set forth in claim 5, wherein the units of pages are units of words.

13. A semiconductor memory device, comprising:

a cell array formed by a plurality of memory cells arranged in a matrix and into which page data including a plurality of main code words is written in units of a plurality of memory cells,

a latch circuit for latching the page data including at least the plurality of main code words,

a data input portion for dividing the page data to be written into a plurality of code words, checking each code word and generating check codes, adding the check codes to corresponding code words to form main code words, and successively transferring the formed main code words to the latch circuit,

a data output portion for receiving the page data including a plurality of main code words having the check codes added thereto transferred from the latch circuit, correcting the error data when there is within a predetermined number of error data for each main code word, adding the corresponding error information for each code word except the check code, and successively outputting the result, and

a control circuit for making the latch circuit write the page data into the cell array all together when page data including a plurality of main code words having the check codes added thereto is latched by the latch circuit, read out the page data including a plurality of code words having the check codes added thereto from the cell array and latch the page data in the latch circuit, and transfer the latch data to the data output portion.

14. A semiconductor memory device as set forth in claim 13, wherein the data input portion includes:

a latch circuit for latching the page data to be written including at least the plurality of main code words,

a plurality of shift registers able to successively shift and hold the code words included in the page data to be written,

a first switch circuit for receiving the page data to be written including code words able to be divided into a plurality of code words and inputting at least successive code words to the different shift registers,

a second switch circuit for selectively outputting the code word data of each shift register in which the code words are all shifted,

a check code generation circuit for checking the code words selected so as to be output by the second switch circuit and generating the check codes, and

an additional circuit for adding the check codes to the code words selectively output by the second switch circuit and outputting the same as the main code words to the latch circuit and

said data output portion includes;

a plurality of shift registers able to successively shift and hold the code words except the check codes included in the read out page data transferred from the latch circuit,

a first switch circuit for receiving the read out page data including the code words divided into a plurality of code words and inputting at least successive code words to different shift registers,

a second switch circuit for selectively outputting the code word data of each shift register into which code words are all shifted,

an error correction circuit for correcting the error data when there is within a predetermined number of error data in the main code words corresponding to the code words output from the second switch circuit, and

an additional circuit for adding the error information from the error correction circuit to the code words selectively output by the second switch circuit and outputting the same.

15. A signal processing system, comprising:

a first semiconductor memory device,

a second semiconductor memory device to which stored data of the first semiconductor memory device is read out, and

a host device for controlling access of the first and second semiconductor memory devices and performing predetermined signal processing according to the data stored in the second semiconductor memory device, wherein

the first semiconductor memory device includes

a cell array formed by a plurality of memory cells arranged in a matrix and into which page data including a plurality of main code words is written in units of a plurality of memory cells,

a latch circuit for latching the page data to be written including at least the plurality of main code words,

a data input portion for dividing the page data to be written into a plurality of code words, checking each code word and generating check codes, adding the check codes to corresponding code words to form main code words, and successively transferring the formed main code words to the latch circuit, and

a control circuit for writing the page data into the cell array all together when the page data including a plurality of main code words added with the check codes are latched by the latch circuit.

16. A signal processing system, comprising:

a first semiconductor memory device,

a second semiconductor memory device to which stored data from the first semiconductor memory device is read out, and

a host device for controlling access to the first and second semiconductor memory devices and performing predetermined signal processing according to the data stored in the second semiconductor memory device, wherein

the first semiconductor memory device includes

a cell array formed by a plurality of memory cells arranged in the matrix and in which page data including a plurality of main code words having check codes are recorded,

a latch circuit for latching page data read out from the cell array,

a data output portion comprising

an input for receiving the page data transferred from the latch circuit,

the plurality of shift registers, arranged in parallel, that successively shift and hold the code words, except the check codes, from the page data transferred from the latch circuit, wherein the plurality of code words are alternately input to different shift registers from among the plurality of shift registers,

a first switch circuit for receiving the read out page data and inputting successive code words to different shift registers from the plurality of shift registers,

a second switch circuit for selectively outputting the code word data from each shift register from the plurality of shift registers,

a correction circuit, positioned in parallel with the plurality of shift registers, that corrects errors in each main code word up to a predetermined number of errors, adding corresponding error information to each code word, except the check code, and outputting the result, and

a control circuit for reading the page data from the cell array, making the latch circuit latch the page data, and transferring the latch data to the data output portion.