Fabrication and use of superlattice

• US 7,407,738 B2
• Filed: 04/02/2004
• Issued: 08/05/2008
• Est. Priority Date: 04/02/2004
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Hewlett-Packard Development Company, L.P. (HP Inc.)
• Inventors: Stasiak, James, Mardilovich, Peter, Kornilovich, Pavel, Thirukkovalur, Niranjan
• Primary Examiner(s): Huff; Mark F.
• Assistant Examiner(s): Sullivan; Caleen O
• Application Number:
  US10/817,729
• Publication Number:
  US 20050221235A1
• Time in Patent Office: 1,586 Days
• Field of Search: 430/322, 430/320, 430/324, 430/296, 430/330, 430/311, 430/313, 430/314
• US Class Current: 430/322
• CPC Class Codes: C23C 4/123 Spraying molten metal
• CPC Class Codes: C23C 4/18 After-treatment
• CPC Class Codes: C30B 29/68 Crystals with laminate structure, e.g. "superlattices"
• CPC Class Codes: G03F 7/40 Treatment after imagewise removal, e.g. baking
• CPC Class Codes: H01L 21/4846 Leads on or in insulating or insulated substrates, e.g. metallisation H01L21/4821 takes precedence; metallisation of ceramics in general C04B41/51; printed circuits H05K3/00
• CPC Class Codes: H01L 21/76838 characterised by the formation and the after-treatment of the conductors etching for patterning the conductors H01L21/3213
• CPC Class Codes: H05K 2203/0117 Pattern shaped electrode used for patterning, e.g. plating or etching
• CPC Class Codes: H05K 2203/025 Abrading, e.g. grinding or sand blasting
• CPC Class Codes: H05K 3/20 by affixing prefabricated conductor pattern H05K1/187, H05K3/046, H05K3/4658, H05K3/4682 takes precedence
• CPC Class Codes: H05K 3/205 using a pattern electroplated or electroformed on a metallic carrier

Abstract

This disclosure relates to a system and method for fabricating and using a superlattice. A superlattice can be fabricated by applying alternating material layers on a ridge and then removing some of the alternating layers to expose edges. These exposed edges can be of nearly arbitrary length and curvature. These edges can be used to fabricate an array of nano-scale-width curved wires.

Claims

1. A method for forming a superlattice comprising:

forming a ridge aver a substrate surface, the ridge comprising sidewalk that are disposed substantially acutely relative to the substrate surface;

applying alternating layers of two or more materials over the ridge; and

removing part of the ridge and the alternating layers to expose edges of the alternating layers at the sidewalls of the ridge.

2. The method of claim 1, wherein the act of forming the ridge comprises:

forming a first layer over the substrate surface;

forming a pattern over the first layer, the pattern having sidewalls disposed substantially acutely relative to the substrate surface; and

removing the first layer and the pattern sufficient to form the ridge from the first layer.

3. The method of claim 2, wherein the act of removing the first layer and the pattern comprises etching the pattern and the first layer.

4. The method of claim 3, wherein the first layer and the pattern comprise materials with different etch rates.

5. The method of claim 4, wherein the etch rate of the first layer'"'"'s material is slower than the etch rare of the pattern'"'"'s material.

6. The method of claim 3, wherein the act of forming the pattern comprises heating the pattern.

7. The method of claim 1 , wherein the act of forming the ridge comprises:

forming the ridge with an electron beam.

8. A method comprising:

applying an etchable surface layer over a substrate;

applying a photoresist layer over the etchable surface layer of the substrate;

exposing parts of the photoresist layer to radiation to create a pattern in the photoresist layer;

removing an unpatterened portion of the photoresist layer;

altering a slope of sidewalls of the patterned photoresist layer; and

etching the photoresist layer and the etchable surface layer to remove the photoresist layer and portions of the etchable surface layer, leaving a sloped, patterned ridge of the etchable surface layer, wherein the sloped patterned ridge is geometrically similar to the sloped, patterned photoresist layer;

applying alternating layers of two or more materials, one of the alternating layers having a thickness between one and one hundred nanometers, over the sloped, patterned ridge; and

removing the alternating layers from a top of the sloped, patterned ridge to expose edges of the alternating layers at the sloped sidewalls of the sloped, patterned ridge.

9. The method of claim 8, wherein the act of applying the etchable surface layer comprises applying an oxide layer.

10. The method of claim 8, wherein the act of applying the etchable surface layer comprises applying the etchable surface layer to a thickness from about one-half micron to five microns.

11. The method of claim 8, wherein the etchable surface layer comprises a PECVD oxide or a nitride.

12. The method of claim 8, wherein the etchable surface layer comprises a low-stress TEOS.

13. The method of claim 8, wherein the act of altering the slope of the sidewalls comprises baking the patterned photoresist layer.

14. The method of claim 8, wherein the act of altering the slope of the sidewalls comprises altering the slope to provide sidewalls defining about a thirty to ninety degree angle relative to the substrate.

15. The method of claim 8, wherein the act of altering the slope of the sidewalls is performed until the sidewalls have about a forty-five degree angle from the substrate.

16. The method of claim 8, wherein the act of etching removes the patterned, photoresist layer at a rate about fifty to 150 percent faster than the etchable surface layer.

17. The method of claim 8, wherein the sloped, patterned ridge is non-linear.

18. The method of claim 8 further comprising:

forming an array of wires having a thickness between one and one hundred nanometers over the exposed edges of one of the alternating layers.

19. A method comprising:

applying alternating layers of two or more materials to a thickness between one and one hundred nanometers over a surface of a substrate having one or more non-linear ridges with substantially sloped side walls; and

planarizing the ridges and the alternating layers to expose edges of the alternating layers at the side walls of the ridges.

20. The method of claim 19, wherein the act of applying comprises chemical-vapor depositing of the alternating layers.

21. The method of claim 19, wherein one of the two or more materials is a conductor or semiconductor and another of the two or more materials is an insulator.

22. The method of claim 19, wherein one of the two or more materials is a conductor having oxidation or nitridation rates, and another of the two or more materials is a conductor having different oxidation or nitridation rates.

23. The method of claim 19, wherein one of the two or more materials has a different etch rate than another of the two or more materials.

24. The method of claim 19, further comprising applying another layer of material over the alternating layers and wherein the planarizing stops when the other layer is removed.

25. The method of claim 19, wherein the act of planarizing comprises chemical-mechanically polishing the ridges and alternating layers.

26. The method of claim 19, further comprising forming an array of non-linear wires with a width between one and one hundred nanometers over the exposed edges atone or more of the alternating layers.

27. The method of claim 26, wherein the act of forming comprises:

electrochemically depositing another material over the exposed edges of one or more of the alternating layers.

28. The method of claim 26, wherein the act of forming comprises:

electrophoretically depositing charged objects over the exposed edges of one or more of the alternating layers.

29. The method of claim 26, wherein the act of forming comprises:

charging ions of another material;

charging the exposed edges of one or more of the alternating layers; and

exposing the charged, exposed edges to the charged ions to build the other material up on the charged, exposed edges.

30. The method of claim 29, wherein the other material comprises a polymer, a semiconductor, an oxide, a metal, or biological molecules.

31. The method of claim 19, further comprising:

off-setting the exposed edges of one or more of the alternating layers to create a corrugated cross-section of the exposed edges of the alternating layers; and

stamping a malleable surface of a second substrate with the offset, exposed edges to create a negative of the off-set exposed edges on the malleable surface.

32. The method of claim 31, further comprising forming an array of non-linear wires having a width between one and one hundred nanometers over the negative on the malleable surface.

33. The method of claim 31, wherein the negative comprises an array of non-linear wires.

34. The method of claim 19, wherein one of the materials is a conductor and another of the materials is an insulator, and further comprising:

off-setting the exposed edges of the conductive-material alternating layer from the exposed edges of the insulative-material alternating layer;

charging objects;

charging the off-set, exposed edges of the conductive-material alternating layer;

exposing the charged, off-set exposed edges to the charged objects to electrophoretically collect the objects in the off-set exposed edges.

35. A method comprising:

shaping a surface layer on a substrate into an elongate ridge that extends along a long axis, the ridge being non-linear along the long axis and comprising a transverse cross section with substantially sloped sidewalls and a top;

applying alternating layers of two or more materials to a thickness between one and one hundred nanometers over the ridge; and

removing the alternating layers from the top of the ridge to expose edges of the alternating layers.

36. The method of claim 35, wherein the act of shaping comprises:

applying a photoresist layer over the surface layer of the substrate;

exposing parts of the photoresist layer to radiation to create a non-linear pattern in the photoresist layer;

removing an unpatterned portion of the photoresist layer;

altering a slope of sidewalls of the non-linear, patterned photoresist layer; and

etching the sloped, non-linear, patterned photoresist layer and the surface layer to remove the non-linear, sloped, patterned photoresist layer and portions of the surface layer to create the non-linear ridge with the gene*ally substantially sloped sidewalls.

37. The method of claim 35, wherein the act of shaping comprises:

stamping the surface layer with a negative of the elongate ridge effective to shape the surface layer to comprise the elongate ridge.

38. The method of claim 35, wherein the act of shaping comprises:

applying an electron beam on the surface layer effective to shape the surface layer to comprise the elongate ridge.

39. The method of claim 35, wherein the act of removing comprises:

planarizing the ridge and the alternating layers.

40. The method of claim 35, further comprising:

forming a wire with a width between one and one hundred nanometers on one of the exposed edges of one of the alternating Layers.

41. The method of claim 35, further comprising:

forming an array of non-linear wires over one or more of the exposed edges of one of the alternating layers.

42. A method comprising:

applying alternating layers of a first material and a second material over a surface of a substrate having one or mare non-linear ridges with substantially sloped side walls;

planarizing the ridges and the alternating layers to expose first edges of the first material layers and second edges of the second material layers at the side walls of the ridges to form a superlattice;

processing the exposed edges to offset the first edges to corrugate the alternating layers of the first material;

providing the superlattice having an array of co-parallel, curved corrugations between about one and one hundred nanometers wide; and

forming an array of co-parallel, curved wires between about one and one hundred nanometers wide using the array of co-parallel, curved corrugations.

43. The method of claim 42, wherein the act of forming comprises depositing a material over the array of co-parallel, curved corrugations and further comprising transferring the array of curved wires onto a substrate.

44. The method of claim 42, wherein the act of providing comprises providing the superlattice having the array of co-parallel, curved corrugations with at least one pitch of the co-parallel, curved corrugations being between about one and one hundred nanometers.

45. The method of claim 42, wherein the act of providing comprises providing the superlattice with the co-parallel, curved corrugations having an elongate dimension between 1000 nanometers and 10 centimeters.

46. The method of claim 42, wherein the act of forming comprises forming the array of co-parallel, curved wires having a pitch between about one and one hundred nanometers.

47. The method of claim 42, wherein the act of providing comprises providing the superlattice having a second array of co-parallel, curved corrugations and the act of forming comprises forming a second array of co-parallel, curved wires.

48. The method of claim 47, wherein the act of forming the first array of wires and the second array of wires comprises forming the first array non-parallel with the second array.

49. The method of claim 47, wherein the act of forming the first array of wires and the second array of wires comprises forming the first array co-parallel with the second array.