Semiconductor pixel arrays with reduced sensitivity to defects

• US 7,408,195 B2
• Filed: 09/04/2003
• Issued: 08/05/2008
• Est. Priority Date: 09/04/2003
• Status: Expired due to Term

• Current Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Original Assignee: Cypress Semiconductor Corporation (Infineon Technologies AG)
• Inventors: Meynants, Guy
• Primary Examiner(s): Ha; Nathan W
• Application Number:
  US10/655,248
• Publication Number:
  US 20050051775A1
• Time in Patent Office: 1,797 Days
• Field of Search: 257/292, 257/E27.133, 257/E27.152, 257 88- 93, 257/444, 257/910, 257/72, 257/59, 257/359, 250/208.1, 348/308, 345 90- 99
• US Class Current: 257/72
• CPC Class Codes: H01L 27/14603 Special geometry or disposition of pixel-elements, address-lines or gate-electrodes
• CPC Class Codes: H01L 27/14643 Photodiode arrays; MOS imagers
• CPC Class Codes: H04N 25/68 applied to defects
• CPC Class Codes: H04N 25/766 comprising control or output lines used for a plurality of functions, e.g. for pixel output, driving, reset or power

Abstract

A pixel structure is described, comprising at least two selection switches coupled in series to improve the yield of the pixel. Also an array comprising such pixel structures logically organized in rows and columns is described, as well as a method for selecting a row or column of pixel structures in such an array.

Claims

1. An array of pixel structures which are logically organized in rows and columns, wherein each pixel structure is associated with a row and a column, each pixel structure comprising:

a photosensitive element; and

a first row selection ON/OFF switch, associated with a first row and coupled to a first row select line for that row, to receive a first row select signal, and a second row selection ON/OFF switch, associated with the first row and coupled to a second row select line for that row, to receive a second row select signal that has a different timing from the first row select signal;

or

a first column selection ON/OFF switch, associated with a first column and coupled to a first column select line for that column, to receive a first column select signal, and a second column selection ON/OFF switch, associated with the first column and coupled to a second column select line for that column, to receive a second column select signal that has a different timing from the first column select signal;

wherein each of the row selection ON/OFF switches or column selection ON/OFF switches is coupled in series between the photosensitive element and a pixel output line.

2. An array according to claim 1, wherein the pixel structures are active pixels.

3. An array according to claim 1, wherein at least one of the two row selection ON/OFF switches or the two column selection ON/OFF switches is a selection transistor.

4. An array according to claim 3, wherein the selection transistor is a MOSFET.

5. An array according to claim 1, wherein the pixel structures are passive pixels.

6. An array according to claim 1, wherein one row or column of pixel structures shares a plurality of select lines, each nth selection ON/OFF switch of the pixel structures on one row or column being connected to an nth select line.

7. An array according to claim 6, wherein the plurality of select lines associated with the one row or column of pixel structures extends in parallel.

8. An array according to claim 1, further comprising at least two drivers, each driver coupled to one of the select lines to drive the coupled select line.

9. An array according to claim 8, wherein the at least two drivers are configured to apply a different select signal to each of the select lines, wherein the select lines are associated with one row or column.

10. An array according to claim 1, wherein one of the select lines is associated with a row or column of pixel structures and is a control line of another row or column of pixel structures.

11. An array according to claim 10, wherein the control line is a reset line.

12. An apparatus, comprising:

means for generating a photoelectric signal charge;

first means for selecting a pixel structure at one or more a distinct row or a distinct column within a pixel via a first select signal;

second means for selecting the pixel structure at one or more of the distinct row or the distinct column via a second signal that has a different timing than the first select signal, the first and second means for selecting coupled in series between the means for generating the photoelectric signal charge and a pixel output line, wherein the first and second means for selecting are both row selection means coupled to different row select lines for the distinct row or both column selection means coupled to different column select lines for the distinct column; and

means for preventing permanent selection of the pixel structure.

13. The apparatus of claim 12, further comprising first means for driving the first means for selecting and second means for driving the second means for selecting.

14. The apparatus of claim 12, further comprising means for resetting a second pixel structure, wherein the means for resetting the second pixel structure is coupled to the first means for selecting.

15. The apparatus of claim 12, further comprising first means for outputting a readout signal from the pixel structure.

16. An apparatus, comprising:

a sensor circuit including a photodiode and a reset transistor, the sensor circuit configured to receive radiation and to output an electrical signal;

a buffer transistor coupled to the sensor circuit to receive the electrical signal from the sensor circuit; and

a selection circuit coupled to the buffer transistor to receive the electrical signal from the buffer transistor, the selection circuit comprising a first selection transistor and a second selection transistor coupled between the buffer transistor and a pixel output line, the first selection transistor coupled to a first select line of a distinct row or a distinct column to receive a first select signal via the first select line, and the second selection transistor coupled to a second select line of the distinct row or the distinct column to receive a second select signal via the second select line, the second select signal being different from the first select signal, wherein the first and second select lines are both row select lines or both column select lines.

17. The apparatus of claim 16, wherein the first and second selection transistors are coupled in series.

18. The apparatus of claim 16, further comprising:

a driver circuit coupled to the first and second select lines to supply the first select signal and the second select signal to the first and second select lines, respectively;

an output line coupled to the selection circuit to receive a readout signal from the selection circuit;

a power supply coupled to the sensor circuit and the buffer transistor to supply a voltage to the sensor circuit and the buffer transistor; and

a second sensor circuit of a second pixel structure, coupled to the first select line, to receive the first select signal and use the first select signal as a reset signal to the second sensor circuit.

19. An array of pixel structures which are logically organized in rows and columns, wherein each pixel structure is associated with a row and a column, and comprises a photosensitive element and at least two row selection ON/OFF switches, each associated with the same row and coupled to a different row select line for that row, or at least two column selection ON/OFF switches, each associated with the same column and coupled to a different column select line for that column, each of the row selection ON/OFF switches or column selection ON/OFF switches coupled in series between the photosensitive element and a pixel output line, wherein each of the row selection ON/OFF switches is configured to receive a same row select signal or each of the column selection ON/OFF switches is configured to receive a same column select signal.

20. An array according to claim 19, wherein one row or column of pixel structures shares a plurality of select lines, each nth selection ON/OFF switch of the pixel structures on one row or column being connected to an nth select line.

21. An array according to claim 19, further comprising at least two drivers, each driver coupled to one of the select lines to drive the coupled select line.