Trench insulated gate field effect transistor

• US 7,408,223 B2
• Filed: 11/26/2004
• Issued: 08/05/2008
• Est. Priority Date: 11/29/2003
• Status: Active Grant

• Current Assignee: Nexperia B.V. (Wingtech Technology Co., Ltd.)
• Original Assignee: NXP B.V. (NXP Semiconductors NV)
• Inventors: Hueting, Raymond J. E.
• Primary Examiner(s): Dickey, Thomas L
• Application Number:
  US10/580,624
• Publication Number:
  US 20070132014A1
• Time in Patent Office: 1,348 Days
• Field of Search: 257/328, 257/333, 257/E29.027, 257/E29.128, 257/E29.133, 257/E29.136, 257/E29.262
• US Class Current: 257/328
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/402 Field plates
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/4232 with insulated gate
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/4238 characterised by the surface lay-out
• CPC Class Codes: H01L 29/7827 Vertical transistors H01L29/7802, H01L29/78642 take precedence
• CPC Class Codes: H01L 29/7831 with multiple gate structure FinFETs or MuGFETs H01L29/7855, thin film transistors H01L29/78645

Abstract

The invention relates to a trench MOSFET with drain (8), sub-channel region (10) body (12) and source (14). The sub-channel region is doped to be the same conductivity type as the body (12), but of lower doping density. A field plate electrode (34) is provided adjacent to the sub-channel region (10) 10 and a gate electrode (32) next to the body (12).

Claims

1. An insulated gate field effect transistor, comprising:

a source region of first conductivity type;

a body region of second conductivity type opposite to the first conductivity type adjacent to the source region;

a sub-channel region of second conductivity type adjacent to the body region, wherein the doping in the body region is at least five times higher than the doping in the sub-channel region;

a drain region of first conductivity type adjacent to the sub-channel region, so that body and sub-channel regions are arranged between the source and drain regions;

insulated trenches extending from the source region through the body region and the sub-channel region to the drain region, each trench having sidewalls, and including insulator on the sidewalls, at least one conductive gate electrode adjacent to the body region, and at least one conductive field plate electrode adjacent to the sub-channel region; and

a gate terminal connected to the gate electrodes and a field plate terminal connected to the field plate electrodes to independently control the voltages on the gate electrodes and field plate electrodes.

2. An insulated gate field effect transistor according to claim 1 wherein the thickness of the insulator adjacent to the field plate electrode is greater than the thickness of the insulator adjacent to the gate electrode.

3. An insulated gate field effect transistor according to claim 1 wherein each trench includes a field plate electrode extending alongside the body region and sub-channel region and a pair of gate electrodes, one on each side of the field plate electrode, adjacent to the body region.

4. An insulated gate field effect transistor according to claim 1 wherein the doping concentration in the sub-channel region is in the range of about 1 ×

10¹⁵ cm<sup>−

3</sup> to about 1 ×

10¹⁶ cm<sup>−

3</sup> and the doping concentration in the body region is in the range of about 5 ×

10¹⁶ cm<sup>−

3</sup> to about 1×

10¹⁸ cm<sup>−

3</sup>.

5. An insulated gate field effect transistor according to claim 1 wherein the doping concentration in the sub-channel region is graded to be higher adjacent to the body region and lower adjacent to the drain region.

6. An insulated gate field effect transistor according to claim 1 having a semiconductor body having opposed first and second major surfaces,

wherein the source region is at the first major surface over the body region, the body region is over the sub-channel region and the sub-channel region is over the drain region, and

the trench extends from the first major surface towards the second major surface through the source, body and sub-channel regions.

7. An insulated gate field effect transistor according to claim 6 wherein the gate is formed of a pair of polysilicon spacers on either side of the field plate electrode.

8. An insulated gate field effect transistor according to claim 6 having an array of cells arranged over the first major surface, the cells including the source region, body region and sub-channel region, and a network of trenches around the cells.

9. Use of an insulated gate field effect transistor, comprising:

a source region of first conductivity type;

a body region of second conductivity type opposite to the first conductivity type adjacent to the source region;

a sub-channel region of second conductivity type adjacent to the body region,

wherein the doping in the body region is at least five times higher than the doping in the sub-channel region;

a drain region of first conductivity type adjacent to the drift region, so that body and drift regions are arranged between the source and drain regions;

insulated trenches extending from the source region through the body region and into the sub-channel region,

the trenches having sidewalls, and including insulator on the sidewalls, at least one conductive gate electrode adjacent to the body region and at least one conductive field plate electrode adjacent to the sub-channel region; and

a gate terminal connected to the gate electrode and a field plate terminal connected to the field plate electrode to independently control the voltages on the gate electrode and field plate electrode, the use comprising the steps of;

applying a voltage to the field plate terminal, the voltage being selected to create an inversion layer in the sub-channel when the transistor is on; and

applying a varying gate voltage to the gate terminal to switch the transistor on and off.