Vertical transistor structure for use in semiconductor device and method of forming the same

• US 7,408,224 B2
• Filed: 02/25/2005
• Issued: 08/05/2008
• Est. Priority Date: 02/25/2004
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Kim, Ji-Young
• Primary Examiner(s): Jackson; Jerome
• Assistant Examiner(s): Diaz; Jose R
• Application Number:
  US11/067,282
• Publication Number:
  US 20050186740A1
• Time in Patent Office: 1,257 Days
• Field of Search: 257/331, 257330-332, 257/520, 257/E29.201
• US Class Current: 257/331
• CPC Class Codes: H01L 29/66621 using etching to form a recess at the gate location etching of semiconductor bodies H01L21/302
• CPC Class Codes: H01L 29/66666 Vertical transistors H01L29/66712, H01L29/66742 take precedence
• CPC Class Codes: H01L 29/7827 Vertical transistors H01L29/7802, H01L29/78642 take precedence
• CPC Class Codes: H10B 12/0335 Making a connection between the transistor and the capacitor, e.g. plug
• CPC Class Codes: H10B 12/053 the transistor being at least partially in a trench in the substrate vertical transistor in combination with a capacitor formed in a substrate trench H10B12/0383
• CPC Class Codes: H10B 12/485 Bit line contacts
• CPC Class Codes: H10B 12/488 Word lines

Abstract

According to some embodiments, a structure of vertical transistor includes gate electrodes distanced by a predetermined interval in an active region, formed in a vertical shape to have a predetermined depth from a top surface of a semiconductor substrate. A gate insulation layer is formed between one side wall of the gate electrode and the substrate. A gate spacer is formed in another sidewall of the gate electrode, covering the gate electrode. A contact plug is formed between the gate spacer. A plug impurity layer is formed in a lower part of the contact plug, and source and drain are formed opposite to the gate electrode within the active region. Thereby, an area occupied by a gate electrode is substantially reduced, so a unit memory cell has a 4F² structure, reducing a memory cell size, by forming a vertical-type gate electrode within an active region.

Claims

1. A vertical transistor structure formed on a semiconductor substrate on which an active region and a non-active region are defined by a shallow trench insulator, the structure comprising:

gate electrodes, which are distanced by a predetermined interval in the active region and are formed in a vertical shape to have a predetermined depth from a top surface of the semiconductor substrate;

a gate insulation layer formed between a first side wall of the gate electrodes and the semiconductor substrate;

a gate spacer formed on a second side wall of the gate electrodes, covering the gate electrodes;

a contact plug, which is formed in the gate spacer and which electrically connects an upper conductive line with the semiconductor substrate;

a plug impurity layer formed in a lower part of the contact plug;

a source/drain formed opposite to the gate electrode within the active region;

a threshold voltage control region for controlling a threshold voltage within the active region, the threshold voltage control region disposed below the source/drain; and

a silicon nitride layer, the silicon nitride layer disposed in contact with a top surface of the gate electrodes, the silicon nitride layer disposed directly over an entirety of the top surface of the gate electrodes.

2. The structure of claim 1, further comprising another contact plug, the another contact plug physically touching the source/drain and electrically connected to a storage node.

3. The structure of claim 1, wherein the gate electrodes are formed of a single layer of polysilicon or of a multilayer having a polycide structure.

4. The structure of claim 1, wherein the gate electrodes are distanced with an interval of about 100 nm to 200 nm, with a depth of about 1500 Å

to 2500 Å

.

5. The structure of claim 1, wherein the gate insulation layer is formed of an oxide layer material and isolates the semiconductor substrate from the gate electrodes.

6. The structure of claim 1, wherein the gate spacer is formed of nitride layer material and separates the gate electrodes from the contact plug.

7. The structure of claim 1, wherein the contact plug is electrically connected to an upper bit line.

8. The structure of claim 1, the plug impurity layer containing n type impurity ions at a density of about 1.0×

10¹³ to 3.0×

10¹³ ions/cm².

9. The structure of claim 1, wherein the source/drain comprises a source region and a drain region that are at equal levels.

10. The structure of claim 1, wherein the source/drain comprises a source region and a drain region and wherein the threshold voltage control region is below both the source region and the drain region.

11. A structure comprising:

a shallow trench insulator disposed in a semiconductor substrate to define an active region and a non-active region of the semiconductor substrate;

gate electrodes disposed in the active region, the gate electrodes having a substantially vertical shape, a lower portion of each of the gate electrodes disposed below a top surface of the semiconductor substrate, the lower portion of each of the gate electrodes representing a majority of the gate electrode;

a gate insulation layer, the gate insulation layer in physical contact with the lower portion of the gate electrodes and in physical contact with the semiconductor substrate from the top surface of the semiconductor substrate to a bottom surface of the gate electrodes;

a gate spacer, the gate spacer in physical contact with a remainder of the lower portion of the gate electrodes that is not in physical contact with the gate insulation layer;

a first contact plug, the first contact plug surrounded by the gate spacer and in physical contact with the gate spacer, the first contact plug electrically connecting an upper conductive line with the semiconductor substrate;

a plug impurity layer, the plug impurity layer disposed in a portion of the semiconductor substrate directly beneath the first contact plug;

source/drain regions, the source/drain regions disposed opposite the gate electrodes in the active region of the semiconductor substrate; and

a first insulation layer disposed on and physically touching the top surface of the semiconductor substrate and a top surface of the shallow trench insulator, the first insulation layer having a first gap, a width of the first gap defining a maximum width of a space occupied by the gate electrodes.

12. The structure of claim 11, further comprising a second contact plug, the second contact plug physically touching one of the source/drain regions.

13. The structure of claim 11, the gate electrodes consisting of a single layer of polysilicon.

14. The structure of claim 11, the gate electrodes having a multiple layer polycide structure.

15. The structure of claim 11, the gate electrodes disposed at a maximum depth from the top surface of the semiconductor substrate, the maximum depth about 1500 Å

to 2500 Å

.

16. The structure of claim 11, the first insulation layer comprising an oxide layer.

17. The structure of claim 11, further comprising a second insulation layer disposed on and physically touching a top surface of the first insulation layer and a top surface of the gate electrodes, the second insulation layer having a second gap, a width of the second gap less than a width of the first gap, the width of the second gap defining a minimum separation between the gate electrodes.

18. The structure of claim 17, the width of the second gap about 100 nm to 200 nm.

19. The structure of claim 17, the second insulation layer comprising a silicon nitride layer.

20. The structure of claim 11, further comprising a threshold voltage control region, the threshold voltage control region disposed in the active region of the semiconductor substrate, the threshold voltage control region separated from the source/drain regions and located below the source/drain regions.