Continuous-time delta-sigma analog digital converter

• US 7,408,494 B2
• Filed: 12/18/2006
• Issued: 08/05/2008
• Est. Priority Date: 12/23/2005
• Status: Active Grant

• Current Assignee: National Semiconductor Germany AG (Texas Instruments, Inc.)
• Original Assignee: National Semiconductor Germany AG (Texas Instruments, Inc.)
• Inventors: Mitteregger, Gerhard
• Primary Examiner(s): Mai; Lam T
• Application Number:
  US11/640,690
• Publication Number:
  US 20070171109A1
• Time in Patent Office: 596 Days
• Field of Search: 341143-155
• US Class Current: 341/143
• CPC Class Codes: H03M 3/37 Compensation or reduction of delay or phase error
• CPC Class Codes: H03M 3/424 the quantiser being a multiple bit one
• CPC Class Codes: H03M 3/454 with distributed feedback, i.e. with feedback paths from the quantiser output to more than one filter stage

Abstract

A continuous-time delta-sigma analog digital converter for converting an analog input signal to a digital output signal, comprising an analog filter with at least one integration capacitor, a cycled quantifier which quantifies the filtered analog signal for generating the digital output signal, and a feedback device with at least one digital analog converter, which supplies at least a first analog feedback signal to the analog filter corresponding to the value of the digital output signal. The feedback device for generating a second feedback signal corresponding to the differentiated output signal of the quantifier, comprises a switching device coupled capacitively to the integration capacitor, by means of which device corresponding charge portions are transmitted to the integration capacitor when there is a variation in the digital output signal.

Claims

1. A continuous-time delta-sigma analog digital converter for converting an analog input signal (IN) to a digital output signal (OUT), comprising:

an analog filter (20) which filters the analog input signal (IN) and has at least one integration capacitor,

a quantifier (30) operated in cycled fashion, which quantifier quantifies the filtered analog signal transmitted by the analog filter for generating the digital output signal (OUT), and

a feedback device (40) with at least one digital analog converter, which device transmits at least a first analog feedback signal to analog filter (20) corresponding to the value of the digital output signal (OUT),

wherein the feedback device (40) comprises a switching device (INV1, INV2) actuated by the digital output signal (OUT) of the quantifier (30) and coupled capacitively (Cc1, Cc2) to the integration capacitor for generating a second feedback signal corresponding to the differentiated output signal of the quantifier (30), by means of which device charge portions are transmitted to the integration capacitor if there is a variation in the digital output signal (OUT), wherein the charge portions correspond to the amount of the variation.

2. The converter according to claim 1, wherein the integration capacitor, which is coupled capacitively to the switching device (INV1, INV2), is part of an integrator (22-3) whose output signal is transmitted directly to the quantifier (30).

3. The converter according to claim 2, wherein the integrator (22-3) is formed by a transconductance element with an integration capacitor connected in series downstream.

4. The converter according to claim 1, wherein the quantifier (30) has a plurality of quantification stages.

5. The converter according to claim 1, wherein the digital output signal (OUT) of the quantifier (30) has a thermometer coding.

6. The converter according to claim 5, wherein the feedback device (40) has a number of feedback paths arranged in parallel with each other corresponding to the thermometer coding, which paths each lead from an output connection of the quantifier (30) via a series connection, comprising an actuatable switching element (INV1, INV2) and a coupling capacitor (Cc1, Cc2), to the integration capacitor.

7. The converter according to claim 1, further compromising a setting circuit (48) which is assigned to the switching device (INV1, INV2), for setting an output characteristic of the switching device (INV1, INV2).

8. The converter according to claim 7, wherein the setting circuit sets an output voltage swing (Vref) of at least one controllable switching element of the switching device (INV1, INV2).

9. The converter according to claim 8, wherein the setting circuit (48) sets the output voltage swing (Vref) of the controllable switching element (INV1, INV2) to a value which is proportional to a voltage (V_SCDACmax) permanently preset by the converter design, which voltage corresponds to a voltage portion (V_SCDAC(t)) acted on by a maximum feedback signal on the integration capacitor.