Minimizing effects of program disturb in a memory device

• US 7,408,810 B2
• Filed: 02/22/2006
• Issued: 08/05/2008
• Est. Priority Date: 02/22/2006
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Aritome, Seiichi, Marquart, Todd
• Primary Examiner(s): AUDUONG, GENE NGHIA
• Application Number:
  US11/359,104
• Publication Number:
  US 20070195603A1
• Time in Patent Office: 895 Days
• Field of Search: 365/185.17, 365/185.18, 365/185.22, 365/185.23, 365/185.02
• US Class Current: 365/185.23
• CPC Class Codes: G11C 16/04 using variable threshold transistors, e.g. FAMOS
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/3418 Disturbance prevention or evaluation; Refreshing of disturbed memory data
• CPC Class Codes: G11C 16/3427 Circuits or methods to prevent or reduce disturbance of the state of a memory cell when neighbouring cells are read or written
• CPC Class Codes: G11C 16/349 Arrangements for evaluating degradation, retention or wearout, e.g. by counting erase cycles
• CPC Class Codes: G11C 29/02 Detection or location of defective auxiliary circuits, e.g. defective refresh counters
• CPC Class Codes: G11C 29/021 in voltage or current generators
• CPC Class Codes: G11C 29/028 with adaption or trimming of parameters

Abstract

A selected word line that is coupled to cells for programming is biased with an initial programming voltage. The unselected wordlines that are adjacent to the selected word line are biased at an initial V_pass. As the quantity of program/erase cycles on the memory device increases, the programming voltage required to successfully program the cells decreases incrementally. V_pass tracks the decrease of the programming voltage.

Claims

1. A method for adjusting an unselected word line bias voltage in a memory device having a memory array comprising a plurality of word lines, the method comprising:

generating an adjusted selected word line bias voltage from an initial selected word line bias;

generating an adjusted unselected word line bias voltage, from an initial unselected word line bias, in response to the adjusted selected word line bias voltage;

biasing a selected word line at the adjusted selected word line bias voltage; and

biasing all unselected word lines at the adjusted unselected word line bias voltage.

2. The method of claim 1 wherein the adjusted unselected word line bias voltage remains at substantially fifty percent of the adjusted selected word line bias voltage.

3. The method of claim 1 wherein the initial selected word line bias is in a range of 16-20V and the initial unselected word line bias is in a range of 9-10V.

4. The method of claim 1 wherein the memory device is a NAND architecture flash memory integrated circuit.

5. The method of claim 1 wherein generating the adjusted selected word line bias voltage comprises decreasing the bias voltage as a quantity of program/erase cycles for the memory array increases.

6. A method for programming a non-volatile memory device having an array of memory cells arranged in rows coupled by word lines and columns coupled by bit lines, the method comprising:

generating an initial selected word line bias that is applied to a row of memory cells of a set of memory cells of the array to be programmed;

generating an initial unselected word line bias that is applied to remaining rows of the set of memory cells;

counting a quantity of program/erase cycles of the set of memory cells;

decreasing the initial selected word line bias by a predetermined voltage as the quantity of program/erase cycles increases; and

decreasing the initial unselected word line bias in response to decreasing the initial selected word line bias.

7. The method of claim 6 wherein the set of memory cells of the array is a memory block.

8. The method of claim 6 wherein decreasing the initial unselected word line bias comprises averaging program voltages that successfully program the set of memory cells during the quantity of program/erase cycles.

9. The method of claim 6 wherein decreasing the initial selected word line bias comprises decreasing the initial selected word line bias in response to the quantity of program/erase cycles.

10. The method of claim 6 and further including biasing selected bit lines at ground potential and biasing unselected bit lines at V_cc.

11. A method for adjusting an unselected word line bias voltage in a memory device having a memory array comprising a plurality of memory blocks, each memory block having a plurality of memory cells arranged in rows that are coupled by word lines, the method comprising:

generating a count of program/erase cycles performed on a first memory block; and

adjusting the unselected word line bias, from an initial unselected word line bias, in response to the count.

12. The method of claim 11 and further comprising:

biasing a selected word line with an initial selected word line bias; and

decreasing the initial selected word line bias incrementally in response to the count of program/erase cycles.

13. The method of claim 11 wherein adjusting the unselected word line bias comprises reducing the bias in increments of 1.0V in response to the count.

14. A non-volatile memory device comprising:

an array of non-volatile memory cells arranged in rows coupled by word lines and columns coupled by bit lines; and

control circuitry coupled to the array of non-volatile memory cells and adapted to execute a method for programming that includes generating an initial programming voltage and an initial unselected word line voltage and decreasing the programming voltage and the unselected word line voltage in response to a quantity of program/erase cycles such that the unselected word line voltage is substantially close to a predetermined percentage of the programming voltage.

15. The device of claim 14 wherein the array of non-volatile memory cells is arranged in a NAND architecture.

16. The device of claim 14 wherein the array of non-volatile memory cells is arranged in a NOR architecture.

17. A non-volatile memory device comprising:

an array of non-volatile memory cells arranged in rows coupled by word lines and columns coupled by bit lines; and

control circuitry coupled to the array of non-volatile memory cells and adapted to execute a method for adjusting V_pass that includes generating an initial V_pass, counting program/erase cycles of the array, and decreasing V_pass in response to the count.

18. The device of claim 17 wherein the control circuitry is further adapted to decrease V_pass by 1.0V each time the count reaches a predetermined quantity of program/erase cycles.

19. A memory system comprising:

a processor for generating memory control signals; and

a flash memory device coupled to the processor, the device comprising;

a memory cell array arranged in rows and columns, each row of cells coupled by a word line and each column of cells coupled by a bit line; and

control circuitry for controlling biasing of the word lines during a program operation wherein the control circuitry is adapted to adjust a selected word line bias from an initial selected word line bias and adjust an unselected word line bias, from an initial unselected word line bias, in response to the selected word line bias wherein the control circuitry biases only the selected word line with the adjusted selected word line bias and all unselected word lines of a memory block being programmed with the adjusted unselected word line bias.

20. The system of claim 19 wherein the control circuitry is further adapted to control biasing of the bit lines such that bit lines coupled to cells to be programmed are biased with 0V.

21. The system of claim 19 wherein the control circuitry is further adapted to control biasing of the bit lines such that bit lines not coupled to the cells to be programed are biased with V_cc.

22. A memory module comprising:

a memory device comprising;

a memory cell array arranged in rows and columns, each row of cells coupled by a word line and each column of cells coupled by a bit line; and

control circuitry for controlling biasing of the word lines of a memory block during a program operation wherein the control circuitry is adapted to adjust a selected word line bias from an initial selected word line bias and adjust an unselected word line bias, from an initial unselected word line bias, in response to the selected word line bias wherein the control circuitry biases only the selected word line of the memory block with the adjusted selected word line bias and all unselected word lines of the memory block with the adjusted unselected word line bias; and

a plurality of contacts configured to provide selective contact between the memory device and a host system.

23. The module of claim 22 and further including a memory controller coupled to the memory device for controlling operation of the memory device in response to the host system.

24. The module of claim 22 wherein the plurality of non-volatile memory cells are flash memory cells.

25. A method for programming a non-volatile memory device having an array of memory cells arranged in rows coupled by word lines and columns coupled by bit lines, the method comprising:

generating an initial selected word line bias that is applied to a row of memory cells of a set of memory cells of the array to be programmed;

generating an initial unselected word line bias that is applied to remaining rows of the set of memory cells;

counting a quantity of program/erase cycles of the set of memory cells;

decreasing the initial unselected word line bias by a predetermined voltage as the quantity of program/erase cycles increases.