Flash controller cache architecture

• US 7,408,834 B2
• Filed: 02/05/2007
• Issued: 08/05/2008
• Est. Priority Date: 03/08/2004
• Status: Active Grant

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: SanDisk Corporation (Western Digital Corporation)
• Inventors: Conley, Kevin M., Elhamias, Reuven
• Primary Examiner(s): Nguyen; Tuan T.
• Application Number:
  US11/671,394
• Publication Number:
  US 20070143545A1
• Time in Patent Office: 547 Days
• Field of Search: 365/230.08, 365/228, 365/230.06
• US Class Current: 365/230.08
• CPC Class Codes: G06F 12/0804 with main memory updating G06F12/0806 takes precedence
• CPC Class Codes: G06F 12/0862 with prefetch
• CPC Class Codes: G06F 12/0866 for peripheral storage systems, e.g. disk cache
• CPC Class Codes: G06F 2212/1016 Performance improvement
• CPC Class Codes: G06F 2212/2022 Flash memory
• CPC Class Codes: G06F 2212/214 Solid state disk
• CPC Class Codes: G06F 2212/2146 being detachable, e.g.. USB memory
• CPC Class Codes: G06F 2212/282 Partitioned cache
• CPC Class Codes: G06F 2212/502 using adaptive policy

Abstract

A buffer cache interposed between a non-volatile memory and a host may be partitioned into segments that may operate with different policies. Cache policies include write-through, write back and read-look-ahead. Write-through and write back policies may improve speed. Read-look-ahead cache allows more efficient use of the bus between the buffer cache and non-volatile memory. A session command allows data to be maintained in volatile memory by guaranteeing against power loss.

Claims

1. A method of handling data streams between a host interface and a flash memory array within a removable memory card using a buffer cache in communication with both the host interface and the flash memory array, comprising:

partitioning the buffer cache into at least a first segment and a second segment;

determining a first caching policy for the first segment; and

determining a second caching policy for the second segment.

2. The method of claim 1 wherein the first caching policy is determined according to characteristics of a first data stream and the second caching policy is determined according to characteristics of a second data stream.

3. The method of claim 1 wherein the first caching policy is a write-through policy.

4. The method of claim 1 wherein the first caching policy is a write-back policy.

5. The method of claim 1 wherein the first caching policy is a read-look-ahead policy.

6. The method of claim 1 further comprising modifying the first segment in size.

7. A method of transferring data from a non-volatile, non-rotating memory array to a host interface in a memory card using a buffer cache disposed between the non-volatile memory array and the host interface, the host interface connecting the memory card to a host, comprising:

receiving a first address range from the host that identifies a first portion of data to be transferred from the non-volatile memory array;

copying the first portion of data from the non-volatile memory array to the buffer cache;

copying a second portion of data from the non-volatile memory array to the buffer cache, the second portion of data not being identified by the host for transfer from the non-volatile memory array; and

sending the first portion of data from the buffer cache to the host while keeping the second portion of data in the buffer cache.

8. The method of claim 7 wherein the second portion of data has a second address range, the first address range and the second address range being sequential.

9. The method of claim 7 wherein the second portion of data is selected to be of the maximum size that allows parallel reading of the second portion of data with the first portion of data from the non-volatile memory array.

10. The method of claim 7 wherein the second portion of data is selected to be of the maximum size that may be stored in the buffer cache or in a segment of the buffer cache.

11. The method of claim 7 further comprising, subsequent to sending the first portion of data from the buffer cache to the host, receiving a third address range that identifies data to be transferred to the host, the third address range identifying at least a third portion of data that is in the second portion of data, the method further comprising transferring the third portion of data directly from the buffer cache to the host and not from the non-volatile memory.