High performance switch fabric element and switch systems

• US 7,408,927 B2
• Filed: 01/06/2004
• Issued: 08/05/2008
• Est. Priority Date: 07/02/1999
• Status: Expired due to Term

• Current Assignee: Marvell Asia Pte Limited (Marvell Technology Group Limited)
• Original Assignee: Qlogic Switch Products Incorporated (Marvell Technology Group Limited)
• Inventors: George, William R.
• Primary Examiner(s): Chan; Wing F.
• Assistant Examiner(s): Jones; Prenell P
• Application Number:
  US10/752,390
• Publication Number:
  US 20040141521A1
• Time in Patent Office: 1,673 Days
• Field of Search: 370/357, 370/256, 370/512, 370/351, 370229-231, 370/412, 370389-395, 370/463, 370/360, 370/439, 370/254, 709/238, 709/243, 709/244, 709/229, 709/245
• US Class Current: 370/360
• CPC Class Codes: H04L 49/101 using crossbar or matrix
• CPC Class Codes: H04L 49/30 Peripheral units, e.g. input or output ports

Abstract

A high performance switch fabric element and flexible link interconnection topologies and frame addressing techniques therefor are disclosed. The fabric element, which may be a 16 port ASIC with internal steerable interconnection among all ports. The fabric element ports each have a unique local routing table, thereby avoiding the need for a global routing table for ports as is provided in the prior art. This also permits addressing and routing from port to port within the fabric element without need for look-up references from off the fabric element, thereby contributing to speed. The fabric element can be used in multiples interconnected by unique link interconnection techniques including cascade, mesh, microstaging, and combinations thereof. These link interconnection techniques provide unique switch topologies that permit high performance switching chassis or network box having a significantly larger number of ports than is achievable with the prior art techniques.

Claims

1. An n-port integrated circuit (IC) switch element, comprising:

n generic ports and an additional generic port to function as a port to an input output processor (IOP), each generic port on the IC switch element including;

an input link to receive data frames from a source off of the IC switch element;

an output link to transmit data frames to a destination off of the IC switch element; and

a steering state machine to direct received data frames from the input link to the output link of one or more of the generic ports on the IC switch element; and

a switch crossbar system to provide an available data channel between each generic port and every other generic port in the IC switch element.

2. The IC switch element of claim 1, wherein the switch crossbar system includes two or more independent crossbars.

3. The IC switch element of claim 1, wherein the switch crossbar system includes:

a frame tag crossbar to allow each generic port to send tags to any one or more of the generic ports on the IC switch element;

a frame request crossbar to allow each generic port to send a frame request to any generic port on the IC switch element from which a tag has been received;

a frame status crossbar to allow each generic port to send additional frame information to any one or more of the generic ports on the IC switch element in response to the frame request; and

a status/frame transfer crossbar to allow each generic port to send preconditioning frame status information for proper frame handling and to send a requested frame to any one or more of the generic ports on the IC switch element in response to the frame request.

4. The IC switch element of claim 1, wherein all of the generic ports on the IC switch element are similar, each generic port including a native identifier to identify a native domain, a native area and a native port for use to steer received data frames.

5. The IC switch element of claim 1, wherein each generic port on the IC switch element includes circuitry to transfer frames via a frame pull transfer methodology such that a source port sends data frames to a destination port when the destination port requests the data frames to prevent head-of-line blocking.

6. The IC switch element of claim 1, wherein the steering state machine is adapted to write multiple tags to multiple generic ports on the IC switch element for multicasting data frames to the multiple generic ports.

7. The IC switch element of claim 1, wherein the steering state machine includes one or more tables, each table having one or more entries, each entry including a valid bit for use to prevent routing of data frames to one or more of the available data channels.

8. The IC switch element of claim 1, wherein the steering state machine includes an alias cache to store selected addresses for broadcasting and multicasting data frames to multiple generic ports on the IC switch element.

9. The IC switch element of claim 1, wherein the steering state machine includes a topology identifier to identify a position of the IC switch element in a topology for parsing the received data frame, a domain steering table to identify a chip path to a desired switch domain, an area steering table to identify a chip path to a desired IC switch element in the desired switch domain, and a port steering table to identify a chip path to a desired port in the desired IC switch element and the desired switch domain.

10. The IC switch element of claim 9, wherein each of the domain steering table, the area steering table and the port steering table have one or more entries, each entry in each table including a valid bit for use in hard zoning to prevent routing of data frames to one or more of the available data channels.

11. The IC switch element of claim 1, wherein the steering state machine includes:

an alias cache to store selected addresses for broadcasting, multicasting and unicasting data frames to multiple generic ports on the IC switch element; and

one or more tables to identify a chip path for a desired data channel for unicasting data frames to a single generic port on the IC switch element when the received data frames do not match an entry in the alias cache.

12. The IC switch element of claim 11, wherein:

the alias cache includes a number of alias cache entries to be compared to a destination frame address; and

the alias cache enables selective steering to one or more generic ports within a selected destination based on a comparison of the alias cache entries to at least part of the destination frame address.

13. The IC switch element of claim 12, wherein the alias cache entries include three bits to enable comparing on Domain ID fields, Area ID fields, and Port ID fields.

14. A switch chassis, including:

a number of chassis ports to connect to ports of devices or ports of other switch chassis; and

at least one n-port integrated circuit (IC) switch element, including;

n generic ports and an additional generic port to function as a port to an input output processor (IOP), each generic port on the IC switch element including;

an input link to receive data frames from a source off of the IC switch element;

an output link to transmit data frames to a destination off of the IC switch element; and

a steering state machine to direct received data frames from the input link to the output link of one or more of the generic ports on the IC switch element; and

a switch crossbar system to provide an available data channel between each generic port and every other generic port in the IC switch element,

wherein at least some of the n generic ports are connected to the number of chassis ports.

15. The switch chassis of claim 14, wherein the at least one IC switch element is one n-port switch element, and each of the n generic ports of the IC switch element is connected to one of the chassis ports to form an n-port switch chassis.

16. The switch chassis of claim 15, wherein the switch chassis is connected to one or more other switch chassis to form a switch network.

17. The switch chassis of claim 14, wherein:

the at least one IC switch element includes multiple n-port switch elements;

for each of the multiple n-port switch elements, the n generic ports include a first group of generic ports and a second group of generic ports;

the switch chassis further including inter-element links formed between the IC switch elements using the first group of generic ports in the multiple n-port switch elements; and

the switch chassis further including data links to the chassis ports formed using the second group of generic ports.

18. The switch chassis of claim 17, wherein the inter-element links are configured in a cascade configuration.

19. The switch chassis of claim 17, wherein the inter-element links are configured in a mesh configuration.

20. The switch chassis of claim 17, wherein the switch chassis is connected to one or more other switch chassis to form a switch network.

21. The switch chassis of claim 14, wherein

the at least one IC switch element includes a first group of n-port switch elements and a second group of n-port switch elements;

for each of the first group of n-port switch elements, the n generic ports include a first group of generic ports and a second group of generic ports;

the switch chassis further including inter-element links formed between the first group of generic ports in the first group of IC n-port switch elements and the generic ports in the second group of n-port switch elements; and

the switch chassis further including data links formed between the chassis ports and the second group of generic ports in the first group of n-port switch elements.

22. The switch chassis of claim 21, wherein:

for each of the first group of IC switch elements, the n generic ports further include a third group of generic ports; and

the switch chassis further includes cascade inter-element links formed between individual elements in the first group of IC switch elements using the third group of generic ports in the first group of IC switch elements.

23. The switch chassis of claim 21, wherein the switch chassis is connected to one or more other switch chassis to form a switch network.

24. The switch chassis of claim 14, wherein the switch crossbar system includes two or more independent crossbars.

25. The switch chassis of claim 24, wherein the switch crossbar system includes:

a frame tag crossbar to allow each generic port to send tags to any one or more of the generic ports on the IC switch element;

a frame request crossbar to allow each generic port to send a frame request to any generic port on the IC switch element from which a tag has been received;

a frame status crossbar to allow each generic port to send additional frame information to any one or more of the generic ports on the IC switch element in response to the frame request; and

a status/frame transfer crossbar to allow each generic port to send preconditioning frame status information for proper frame handling and to send a requested frame to any one or more of the generic ports on the IC switch element in response to the frame request.