Method for transmitting data

• US 7,408,951 B1
• Filed: 05/10/2004
• Issued: 08/05/2008
• Est. Priority Date: 01/20/2004
• Status: Active Grant

• Current Assignee: Tellabs Petaluma, Inc. (Infinera Corp.)
• Original Assignee: Tellabs Petaluma, Inc. (Infinera Corp.)
• Inventors: O'Connor, Paul E., Huang, Shuo, Ripy, Paul B.
• Primary Examiner(s): Rao; Seema S.
• Assistant Examiner(s): Russell; Wanda Z
• Application Number:
  US10/842,840
• Time in Patent Office: 1,548 Days
• Field of Search: 370/307, 370/463, 725/68, 725/131, 725/151, 711/217, 710 52- 57, 710/310
• US Class Current: 370/463
• CPC Class Codes: H04L 47/34 ensuring sequence integrity, e.g. using sequence numbers
• CPC Class Codes: H04L 47/50 Queue scheduling
• CPC Class Codes: H04L 49/3081 ATM peripheral units, e.g. policing, insertion or extraction
• CPC Class Codes: H04L 49/40 Constructional details, e.g. power supply, mechanical construction or backplane
• CPC Class Codes: H04L 49/405 Physical details, e.g. power supply, mechanical construction or backplane of ATM switches

Abstract

Communications equipment includes a demultiplexer that controllably delivers portions of the data to buffers in a particular order, a logic circuit that selectively controls the transmission of the data from the buffers such that a transmission order of the data portions is preserved, and transmission circuits, each in communication with at least one of the buffers. A method of transmitting data is further disclosed.

Claims

1. A communications device comprising:

a plurality of buffers, each configured to receive and store data;

a demultiplexer configured to distribute consecutive portions of a data signal among the plurality of buffers in a predetermined order; and

a logic circuit configured to output a mask signal,

wherein the mask signal is based on a previous state of the mask signal, and

wherein each of the plurality of buffers is configured to output a stored portion of the data signal according to a corresponding bit of the mask signal.

2. The communications device according to claim 1, wherein the mask signal is based on a previous output state of each of the plurality of buffers.

3. The communications device according to claim 1, wherein the plurality of buffers is configured to output the stored portions in the same order as distributed by the demultiplexer.

4. The communications device according to claim 1, wherein each of the plurality of buffers is coupled to a corresponding one of a plurality of transmission circuits, and

wherein each transmission circuit is configured to output a serial data signal including the corresponding outputted stored portion.

5. The communications device according to claim 1, wherein the demultiplexer comprises a counter and wherein the order of distribution is determined by an output of the counter.

6. The communications device according to claim 5, wherein the counter comprises a modulo counter.

7. The communications device according to claim 1, wherein the data signal comprises at least one ATM cell.

8. The communications device according to claim 1, wherein each of the plurality of buffers is configured to retain the stored portion when the corresponding bit of the mask signal has a first logical state, and

wherein each of the plurality of buffers is configured to output the stored portion when the corresponding bit of the mask signal has a second logical state different than the first logical state.

9. The communications device according to claim 1, wherein each of the plurality of buffers is configured to hold m ATM cells, where m is an integer greater than zero.

10. The communications device according to claim 1, said device comprising a plurality of transmission channels, each channel corresponding to one of the plurality of buffers,

wherein, onto each of the plurality of transmission channels, at least one of the corresponding buffer, the logic circuit, and a corresponding transmission circuit is configured to output a signal based on the stored portion when the corresponding bit of the mask signal has a first logical state, and to output an idle cell when the corresponding bit of the mask signal has a second logical state different than the first logical state.

11. The communications device according to claim 10, wherein, for each of the plurality of transmission channels, at least one of the corresponding buffer, the logic circuit, and the corresponding transmission circuit is configured to output an idle cell when the buffer is empty.

12. The communications device according to claim 1, said device comprising a multiplexer configured to output a second data signal comprising the outputted stored portions in the same order as distributed by the demultiplexer.

13. The communications device according to claim 12, said device comprising an ATM queue configured to receive a signal based on the second data signal.

14. The communications device according to claim 12, wherein the multiplexer comprises a counter.

15. The communications device according to claim 12, wherein each of the demultiplexer and the multiplexer includes a counter, and

wherein an operation of the counter of the multiplexer is synchronized to an operation of the counter of the demultiplexer.

16. The communications device according to claim 1, said device comprising:

a backplane comprising a plurality of transmission channels, each of the plurality of transmission channels corresponding to one of the plurality of buffers; and

a plurality of card slots, each card slot being in electrical communication with the backplane and configured to conduct, for at least one of the plurality of buffers and to the corresponding transmission channel, a signal based on the outputted stored portion.

17. A communications device comprising:

a plurality of buffers, each configured to receive and store data;

a demultiplexer configured to distribute consecutive portions of a data signal among the plurality of buffers in a predetermined order; and

a logic circuit configured to output a mask signal,

wherein the mask signal is based on a previous output state of each of the plurality of buffers, and

wherein each of the plurality of buffers is configured to output a stored portion of the data signal according to a corresponding bit of the mask signal.

18. The communications device according to claim 17, wherein the plurality of buffers is configured to output the stored portions in the same order as distributed by the demultiplexer.

19. The communications device according to claim 17, wherein each of the plurality of buffers is coupled to a corresponding one of a plurality of transmission circuits, and

wherein each transmission circuit is configured to output a serial data signal including the corresponding outputted stored portion.

20. The communications device according to claim 17, wherein the demultiplexer comprises a counter and wherein the order of distribution is determined by an output of the counter.

21. The communications device according to claim 17, wherein each of the plurality of buffers is configured to retain the stored portion when the corresponding bit of the mask signal has a first logical state, and

wherein each of the plurality of buffers is configured to output the stored portion when the corresponding bit of the mask signal has a second logical state different than the first logical state.

22. The communications device according to claim 17, said device comprising a plurality of transmission channels, each channel corresponding to one of the plurality of buffers,

wherein, onto each of the plurality of transmission channels, at least one of the corresponding buffer, the logic circuit, and a corresponding transmission circuit is configured to output a signal based on the stored portion when the corresponding bit of the mask signal has a first logical state, and to output an idle cell when the corresponding bit of the mask signal has a second logical state different than the first logical state.

23. The communications device according to claim 17, said device comprising a multiplexer configured to output a second data signal comprising the outputted stored portions in the same order as distributed by the demultiplexer.

24. A method of transmitting data, said method comprising:

distributing consecutive portions of a data signal among a plurality of buffers in a predetermined order,

storing each of the distributed portions in the respective buffer;

outputting a mask signal; and

outputting each of the stored portions according to a corresponding bit of the mask signal,

wherein the mask signal is based on a previous state of the mask signal.

25. The method of transmitting data according to claim 24, wherein the mask signal is based on a previous output state of each of the plurality of buffers.

26. The method of transmitting data according to claim 24, wherein said outputting each of the stored portions comprises outputting the stored portions in the same order as distributed.

27. The method of transmitting data according to claim 24, wherein said outputting each of the stored portions further comprises outputting a serial data signal including the corresponding outputted stored portion.

28. The method of transmitting data according to claim 24, wherein said distributing is performed according to an output of a modulo counter.

29. The method of transmitting data according to claim 24, wherein the consecutive portions each comprise an ATM cell.

30. The method of transmitting data according to claim 24, wherein said outputting each of the stored portions comprises retaining the stored portion when the corresponding bit of the mask signal has a first logical state, and outputting the stored portion when the corresponding bit of the mask signal has a second logical state different than the first logical state.

31. The method of transmitting data according to claim 24, wherein said outputting each of the stored portions comprises outputting, onto each of a plurality of transmission channels, each channel corresponding to one of the plurality of buffers, a signal based on the stored portion when the corresponding bit of the mask signal has a first logical state;

and outputting, onto each of the plurality of transmission channels, an idle cell when the corresponding bit of the mask signal has a second logical state different than the first logical state.

32. The method of transmitting data according to claim 31, wherein said outputting each of the stored portions comprises, for each of the plurality of transmission channels, outputting an idle cell when the buffer is empty.

33. The method of transmitting data according to claim 24, said method comprising:

receiving a signal based on the stored portions; and

outputting a second data signal comprising the received stored portions in the same order as distributed.

34. The method of transmitting data according to claim 33, said method comprising receiving the outputted stored portions,

wherein said receiving is synchronized to said distributing.

35. A machine-readable medium comprising machine-executable instructions for performing a method of transmitting data, said method comprising:

distributing consecutive portions of a data signal among a plurality of buffers in a predetermined order,

storing each of the distributed portions in the respective buffer;

outputting a mask signal; and

outputting each of the stored portions according to a corresponding bit of the mask signal,

wherein the mask signal is based on a previous state of the mask signal.

36. The medium according to claim 35, wherein the mask signal is based on a previous output state of each of the plurality of buffers.