Digital filter

• US 7,408,983 B2
• Filed: 01/06/2005
• Issued: 08/05/2008
• Est. Priority Date: 01/09/2004
• Status: Expired due to Fees

• Current Assignee: LG Electronics, Inc. (LG Corporation)
• Original Assignee: LG Electronics, Inc. (LG Corporation)
• Inventors: Kim, Woo Chan
• Primary Examiner(s): Payne; David C.
• Assistant Examiner(s): Flores; Leon
• Application Number:
  US11/029,508
• Publication Number:
  US 20050152444A1
• Time in Patent Office: 1,307 Days
• Field of Search: 375229- 34
• US Class Current: 375/232
• CPC Class Codes: H03H 17/0223 Computation saving measures; Accelerating measures computations per se G06F
• CPC Class Codes: H03H 17/0294 Variable filters; Programmable filters
• CPC Class Codes: H03H 21/0012 Digital adaptive filters

Abstract

Disclosed is a digital filter with a combined architecture of a 4-tap real valued filter and a-tap complex valued filter, whereby the filter size is reduced and no output delay is occurred due to the filter operations. According to the present invention, the digital filter is operated either in real valued filter mode or complex valued filter mode according to a mode selection signal, a filter output is obtained within one clock according to an operation selection signal, and an operator performs operations twice within one symbol clock (i.e., a time period) unlike a related art filter in which an operator performs the operation only once for each symbol clock. Therefore, the present invention filter is capable of resolving the filter size problem by substantially reducing the number of multipliers and adders.

Claims

1. A digital filter comprising:

a control unit for generating and outputting a mode selection signal through which the operations of a real valued filter and a complex valued filter are determined, and an operation selection signal for controlling corresponding operators perform the operations twice for a symbol clock (clk), the operation selection signal being generated by delaying a clock with a ½

phase difference from the clk by a predetermined time;

a data input unit for selecting an input real valued data and an input imaginary valued data according to the mode selection signal, delaying the data, respectively, selecting the input data and delayed data again according to the mode selection signal and the operation selection signal, and outputting the selected data for coefficient update and filter output;

a first coefficient update unit for multiplying the selected output data from the data input unit by an error value that is selected according to the mode selection signal and the operation selection signal, adding the multiplication result to an old coefficient that is selected according to the mode selection signal and the operation selection signal and thereby, updating two coefficients of the real valued filter and a real coefficient of the complex valued filter within one clock;

a second coefficient update unit for multiplying the selected output data from the data input unit by an error value that is selected according to the mode selection signal and the operation selection signal, adding the multiplication result to an old coefficient that is selected according to the mode selection signal and the operation selection signal and thereby, updating two coefficients of the real valued filter and a real coefficient of the complex valued filter within one clock;

a first filter output unit for multiplying two data selectively outputted from the data input unit for a clock by the two coefficients of the real valued filter or the real coefficient of the complex valued filter provided from the first coefficient update unit and thereby, generating two tap outputs of the real valued filter or two outputs of the complex valued filter; and

a second filter output unit for multiplying two data selectively outputted from the data input unit for a clock by the two coefficients of the real valued filter or the real coefficient of the complex valued filter provided from the second coefficient update unit and thereby, generating two tap outputs of the real valued filter or two outputs of the complex valued filter.

2. The digital filter according to claim 1, wherein the data input unit is comprised of:

a first data selection part for selecting within a clock a delayed real valued data and a delayed imaginary valued data, each being delayed by a predetermined period, according to the mode selection signal, and outputting the selected two data to the first coefficient update unit;

a second data selection pan for delaying a delayless input real valued data and a delayless input imaginary valued, data, respectively, selecting two data among the input data and the delayed data within a clock according to the, mode selection signal and the operation selection signal, and outputting the selected two data to the first filter output unit;

a third data selection part for selecting within a clock a delayed real valued data and a delayed imaginary valued data, each being delayed by a predetermined period, according to the mode selection signal, and outputting the selected two data to the second coefficient update unit; and

a fourth data selection part for delaying a delayless input real valued data, a delayless input imaginary valued data, and input data from the second data selection part, respectively, selecting two data among the input data and the delayed data within a clock according to the mode selection signal and the operation selection signal, and outputting the selected two data to the second filter output unit.

3. The digital filter according to claim 2, wherein the first data selection part is comprised of:

a first delay for delaying a delayed real valued input data synchronously with the clk;

a first selector for selectively outputting, according to the mode selection signal, one of delayed imaginary valued input data and the delayed real valued data provided from the first delay;

a second delay for delaying the output data from the first selector synchronously with the clk;

a second selector for selectively outputting, according to the mode selection signal, one of the output data from the second data selection part and the delayed real valued data provided from the first delay;

a third selector for selectively outputting, according to the mode selection signal, one of the output data from the second data selection part and the delayed data provided from the second delay; and

a fourth selector for sequentially outputting, according to the operation selection signal, the output data from the second and third selectors to the first coefficient update unit for a clk.

4. The digital filter according to claim 1, wherein the second data selection part is comprised of:

a first delay for delaying a delayless real valued input data synchronously with the clk;

a first selector for selectively outputting, according to the mode selection signal, one of delayless imaginary valued input data and the delayed real valued data provided from the first delay;

a second delay for delaying the output data from the first selector synchronously with the clk;

a second selector for selectively outputting, according to the mode selection signal, one of the output data from the second data selection part and the delayed real valued data provided from the first delay;

a third selector for selectively outputting, according to the mode selection signal, one of the delayed data from the first delay and the delayed data from the second delay; and

a fourth selector for sequentially outputting, according to the operation selection signal, the output data from the second and third selectors to the first coefficient update unit for a clk.

5. The digital filter according to claim 2, wherein the third data selection part is comprised of:

a first selector for selectively outputting, according to the mode selection signal, one of delayed imaginary valued input data and the delayed data provided from the second delay of the first data selection part;

a first delay for delaying the output data from the first selector synchronously with the clk;

a second selector for selectively outputting, according to the mode selection signal, one of delayed real valued input data and the delayed real valued data provided from the first delay;

a second delay for delaying the output data from the second selector synchronously with the clk;

a third selector for selectively outputting, according to the mode selection signal, one of the output data from the fourth data selection part and the delayed imaginary valued data provided from the first delay;

a fourth selector for selectively outputting, according to the mode selection signal, one of the output data from the fourth data selection part and the delayed data provided from the second delay; and

a fifth selector for sequentially outputting, according to the operation selection signal, the output data from the third and fourth selectors to the second coefficient update unit for a clk.

6. The digital filter according to claim 2, wherein the fourth data selection part is comprised of:

a first selector for selectively outputting, according to the mode selection signal, one of delayless imaginary valued input data and the delayed data provided from the second delay of the second data selection part;

a first delay for delaying the output data from the first selector synchronously with the clk;

a second selector for selectively outputting, according to the mode selection signal, one of delayless real valued input data and the delayed real valued data provided from the first delay;

a second delay for delaying the output data from the second selector synchronously with the clk;

a third selector for selectively outputting, according to the mode selection signal, one of the output data from the first selector and the output data from the first delay;

a fourth selector for selectively outputting, according to the mode selection signal, one of the delayed data from the first delay and the delayed data from the second delay; and

a fifth selector for sequentially outputting, according to the operation selection signal, the output data from the third and fourth selectors to the second filter output unit for a clk.

7. The digital filter according to claim 1, wherein the first coefficient update unit is comprised of:

a first selector for sequentially outputting, according to the operation selection signal, a real valued input error and an imaginary valued input error for a clk;

a second selector for selectively outputting, according to the mode selection signal, one of a real valued input error and the output data from the first selector;

a multiplier for multiplying the output data from the first data selection part by the output data from the second selector;

a first gain part for multiplying the output from the multiplier by a gain constant A;

a third selector for selectively outputting, according to the mode selection signal, one of the output data from the multiplier and the output data from the gain part;

a first adder for adding the output data from the third selector to an old feedback coefficient;

a saturator for limiting the addition result of the first adder if the addition result exceeds a predetermined value;

a first delay for delaying the output data from the saturator synchronously with a clk with a ½

phase difference from the clk;

a second delay for delaying the output data from the saturator synchronously with the clk;

a fourth selector for sequentially outputting, according to the operation selection signal, the delayed data from the first and second delays for a clk;

a fifth selector for selectively outputting, according to the mode selection signal, one of the output data from the fourth selector and the output data from the second delay;

a second gain part for dividing the output data from the fifth selector by a gain constant C;

a second adder for adding the output data from the first and the second delay;

a sixth selector for sequentially outputting, according to the operation selection signal, a constant ‘

0’ and

the output data from the second adder for a clk; and

a seventh selector for selecting, according to the mode selection signal, one of the output data from the sixth selector and the output data from the fourth selector, and outputting the selected data to the first adder as an old coefficient.

8. The digital filter according to claim 7, wherein the saturator is comprised of:

a code extractor for extracting a code out of the output data from the first adder;

a comparer for taking an absolute value of the output data from the first adder, and comparing whether the absolute value is greater than a predetermined constant B;

an eighth selector for selecting a positive constant B if a positive code is detected by the code extractor, and selecting a negative constant −

B if a negative code is detected by the code extractor; and

a ninth selector for outputting the output from the eighth selector if the absolute value is greater than the constant B, and selecting the output from the first adder if the absolute value is greater than the constant B, and outputting the selected value to the first and second delays.

9. The digital filter according to claim 1, wherein the second coefficient update unit is comprised of:

a first selector for sequentially outputting, according to the operation selection signal, a real valued input error and an imaginary valued input error for a clk;

a second selector for selectively outputting, according to the mode selection signal, one of a real valued input error and the output data from the first selector;

a multiplier for multiplying the output data from the third data selection part by the output data from the second selector;

a third gain part for multiplying the output from the multiplier by a gain constant A;

a third selector for selectively outputting, according to the mode selection signal, one of the output data from the multiplier and the output data from the gain part;

an adder for adding the output data from the third selector to an old feedback coefficient;

a saturator for limiting the addition result of the adder if the addition result exceeds a predetermined value;

a first delay for delaying the output data from the saturator synchronously with a clk with a ½

phase difference from the clk;

a second delay for delaying the output data from the saturator synchronously with the clk;

a fourth selector for sequentially outputting, according to the operation selection signal, the delayed data from the first and second delays for a clk;

a fifth selector for selectively outputting, according to the mode selection signal, one of the output data from the fourth selector and the output data from the second delay;

a fourth gain part for dividing the output data from the fifth selector by a gain constant C;

a subtracter for obtaining a difference between the delayed data provided from the first delay and the delayed data provided from the second delay;

a sixth selector for sequentially outputting, according to the operation selection signal, a constant ‘

0’ and

the output data from the subtracter for a clk; and

a seventh selector for selecting, according to the mode selection signal, one of the output data from the sixth selector and the output data from the fourth selector, and outputting the selected data to the adder as an old coefficient.

10. The digital filter according to claim 9, wherein the saturator is comprised of:

a code extractor for extracting a code out of the output data from the adder;

a comparer for taking an absolute value of the output data from the adder, and comparing whether the absolute value is greater than a predetermined constant B;

an eighth selector for selecting a positive constant B if a positive code is detected by the code extractor, and selecting a negative constant −

B if a negative code is detected by the code extractor; and

a ninth selector for outputting the output from the eighth selector if the absolute value is greater than the constant B, and selecting the output from the first adder if the absolute value is greater than the constant B, and outputting the selected value to the first and second delays.

11. The digital filter according to claim 1, wherein the first filter output unit is comprised of:

a multiplier for multiplying an output coefficient from the first coefficient update unit by the output data from the second data selection part; and

a delay for delaying the output data from the multiplier synchronously with a clk with a ¼

phase difference from the clk, wherein the output from the delay is designated as a first output, and the output from the multiplier is designated as a second output.

12. The digital filter according to claim 1, wherein the second filter output unit is comprised of:

a multiplier for multiplying an output coefficient from the second coefficient update unit by the output-data from the fourth data selection part; and

a delay for delaying the output data from the multiplier synchronously with a clk with a ¼

phase difference from the clk, wherein the output from the delay is designated as a third output; and

the output from the multiplier is designated as a fourth output.

13. The digital filter according to claim 11 or claim 12, wherein if the digital filter is operated as a real valued filter according to the mode selection signal, the first to fourth outputs are summed up in a predetermined summation period and outputted as a final real valued filter output.

14. The digital filter according to claim 11 or claim 12, wherein if the digital filter is operated as a complex valued filter according to the mode selection signal, in the predetermined summation period a real valued filter output is obtained from a difference between the first output and the third output and a complex valued filter output is obtained from a sum of the second output and the fourth output.

15. A digital filter comprising:

a control unit for generating and outputting a mode selection signal through which the operations of a real valued filter and a complex valued filter are determined, and an operation selection signal for controlling corresponding operators perform the operations twice for a symbol clock (clk), the operation selection signal being generated by delaying a clock with a ½

phase difference from the clk by a predetermined time;

a data input unit for selecting an input real valued data and an input imaginary valued data according to the mode selection signal, delaying the data, respectively, selecting the input data and delayed data again according to the mode selection signal and the operation selection signal, and outputting the selected data for coefficient update and filter output;

a first coefficient update unit for multiplying the selected output data from the data input unit by an error value that is selected according to the mode selection signal and the operation selection signal, adding the multiplication result to an old coefficient that is selected according to the mode selection signal and the operation selection signal and thereby, updating two coefficients of the real valued filter and a real coefficient of the complex valued filter within one clock;

a second coefficient update unit for multiplying the selected output data from the data input unit by an error value that is selected according to the mode selection, signal and the operation selection signal, adding the multiplication result to an old coefficient that is selected according to the mode selection signal and the operation selection signal and thereby, updating two coefficients of the real valued filter and a real coefficient of the complex valued filter within one clock;

a first filter output unit for multiplying two data selectively outputted from to data input unit for a clock by the two coefficients of the real valued filter or the real coefficient of the complex valued filter provided from the first coefficient update unit and thereby, generating two tap outputs of the real valued filter or two outputs of the complex valued filter;

a second filter output unit for multiplying two data selectively outputted from the data input unit for a clock by the two coefficients of the real valued filter or the real coefficient of the complex valued filter provided from the second coefficient update unit and thereby, generating two tap outputs of the real valued filter or two outputs of the complex valued filter; and

a final output unit for producing a final output of a tap real valued filter by adding all the outputs from the first and second filter output units if the mode selection signal indicates that the digital filter is in real valued filter mode, and producing a final output of a 1-tap complex valued filter, the final output being composed of a real valued output and an imaginary valued output, by adding or subtracting the outputs from the first and second output units together.

16. The digital filter according to claim 15, wherein the data input wait is comprised of:

a first data selection part for selecting within a clock a delayed real valued data and a delayed imaginary valued data, each being delayed by a predetermined period, according to the mode selection signal, and outputting the selected two data to the first coefficient update unit;

a second data selection part for delaying a delayless input real valued data and a delayless input imaginary valued data, respectively, selecting two data among the input data and the delayed data within a clock according to the mode selection signal and the operation selection signal, and outputting the selected two data to the first filter output unit;

a third data selection part for selecting within a clock a delayed real valued data and a delayed imaginary valued data, each being delayed by a predetermined period, according to the mode selection signal, and outputting the selected two data to the second coefficient update unit; and

a fourth data selection part for delaying a delayless input real valued data, a delayless input imaginary valued data, and input data from the second data selection part, respectively, selecting two data among the input data and the delayed data within a clock according to the mode selection signal and the operation selection signal, and outputting the selected two data to the second filter output unit.

17. The digital filter according to claim 16, wherein the first data selection part is comprised of:

a first delay for delaying a delayed real valued input data synchronously with the clk;

a first selector for selectively outputting, according to the mode selection signal, one of delayed imaginary valued input data and the delayed real valued data provided from the first delay;

a second delay for delaying the output data from the first selector synchronously with the clk;

a second selector for selectively outputting, according to the mode selection signal, one of the output data from the second data selection part and the delayed real valued data provided from the first delay;

a third selector for selectively outputting, according to the mode selection signal, one of the output data from the second data selection part and the delayed data provided from the second delay; and

a fourth selector for sequentially outputting, according to the operation selection signal, the output data from the second and third selectors to the first coefficient update unit for a clk.

18. The digital filter according to claim 16, wherein the second data selection part is comprised of:

a first delay for delaying a delayless real valued input data synchronously with the clk;

a first selector for selectively outputting, according to the mode selection signal, one of delayless imaginary valued input data and the delayed real valued data provided from the first delay;

a second delay for delaying the output data from the first selector synchronously with the clk;

a second selector for selectively outputting, according to the mode selection signal, one of the output data from the second data selection part and the delayed real valued data provided from the first delay;

a third selector for selectively outputting, according to the mode selection signal, one of the delayed data from the first delay and the delayed data from the second delay; and

a fourth selector for sequentially outputting, according to the operation selection signal, the output data from the second and third selectors to the first coefficient update unit for a clk.

19. The digital filter according to claim 16, wherein the third data selection part is comprised of:

a first selector for selectively outputting, according to the mode selection signal, one of delayed imaginary valued input data and the delayed data provided from the second delay of the first data selection part;

a first delay for delaying the output data from the first selector synchronously with the clk;

a second selector for selectively outputting, according to the mode selection signal, one of delayed real valued input data and the delayed real valued data provided from the first delay;

a second delay for delaying the output data from the second selector synchronously with the clk;

a third selector for selectively outputting, according to the mode selection signal, one of the output data from the fourth data selection part and the delayed imaginary valued data provided from the first delay;

a fourth selector for selectively outputting, according to the mode selection signal, one of the output data from the fourth data selection part and the delayed data provided from the second delay; and

a fifth selector for sequentially outputting, according to the operation selection signal, the output data from the third and fourth selectors to the second coefficient update unit for a clk.

20. The digital filter according to claim 16, wherein the fourth data selection part is comprised of:

a first selector for selectively outputting, according to the mode selection signal, one of delayless imaginary valued input data and the delayed data provided from the second delay of the second data selection part;

a first delay for delaying the output data from the first selector synchronously with the clk;

a second selector for selectively outputting, according to the mode selection signal, one of delayless real valued input data and the delayed real valued data provided from the first delay;

a second delay for delaying the output data from the second selector synchronously with the clk;

a third selector for selectively outputting, according to the mode selection signal, one of the output data from the first selector and the output data from the first delay;

a fourth selector for selectively outputting, according to the mode selection signal, one of the delayed data from the first delay and the delayed data from the second delay; and

a fifth selector for sequentially outputting, according to the operation selection signal, the output data from the third and fourth selectors to the second filter output unit for a clk.

21. The digital filter according to claim 15, wherein the first coefficient update unit is comprised of:

a first selector for sequentially outputting, according to the operation selection signal, a real valued input error and an imaginary valued input error for a clk;

a second selector for selectively outputting, according to the mode selection signal, one of a real valued input error and the output data from the first selector;

a multiplier for multiplying the output data from the first data selection part by the output data from the second selector;

a first gain part for multiplying the output from the multiplier by a gain constant A;

a third selector for selectively outputting, according to the mode selection signal, one of the output data from the multiplier and the output data from the gain part;

a first adder for adding the output data from the third selector to an old feedback coefficient;

a saturator for limiting the addition result of the first adder if the addition result exceeds a predetermined value;

a first delay for delaying the output data from the saturator synchronously with a clk with a ½

phase difference from the clk;

a second delay for delaying the output data from the saturator synchronously with the clk;

a fourth selector for sequentially outputting, according to the operation selection signal, the delayed data from the first and second delays for a clk;

a fifth selector for selectively outputting, according to the made selection signal, one of the output data from the fourth selector and the output data from the second delay;

a second gain part for dividing the output data from the fifth selector by a gain constant C;

a second ader for adding the output data from the first and the second delay;

a sixth selector for sequentially outputting, according to the operation selection signal, a constant ‘

0’ and

the output data from the second adder for a clk; and

a seventh selector for selecting, according to the mode selection signal, one of the output data from the sixth selector, and the output data from the fourth selector, and outputting the selected data to the first adder as an old coefficient.

22. The digital filter according to claim 15, wherein the second coefficient update unit is comprised of:

a first selector for sequentially outputting, according to the operation selection signal, a real valued input error and an imaginary valued input error for a clk;

a second selector for selectively outputting, according to the mode selection signal, one of a real valued input error and the output data from the first selector;

a multiplier for multiplying the output data from the third data selection part by the output data from the second selector;

a third gain part for multiplying the output from the multiplier by a gain constant A;

a third selector for selectively outputting, according to the mode selection signal, one of the output data from the multiplier and the output data from the gain part;

an adder for adding the output data from the third selector to an old feedback coefficient;

a saturator for limiting the addition result of the adder if the addition result exceeds a predetermined value;

a first delay for delaying the output data from the saturator synchronously with a clk with a ½

phase difference from the clk;

a second delay for delaying the output data from the saturator synchronously with the clk;

a fourth selector for sequentially outputting, according to the operation selection signal, the delayed data from the first and second delays for a clk;

a fifth selector for selectively outputting, according to the mode selection signal, one of the output data from the fourth selector and the output data from the second delay;

a fourth gain part for dividing the output data from the fifth selector by a gain constant C;

a subtracter for obtaining a difference between the delayed data provided from the first delay and the delayed data provided from the second delay;

a sixth selector for sequentially outputting, according to the operation selection signal, a constant ‘

0’ and

the output data from the subtracter for a clk; and

a seventh selector for selecting, according to the mode selection signal, one of the output data from the sixth selector and the output data from the fourth selector, and outputting the selected data to the adder as an old coefficient.

23. The digital filter according to claim 15, wherein the first filter output unit is comprised of:

a multiplier for multiplying an output coefficient from the first coefficient update unit by the output data from the second data selection part; and

a delay for delaying the output data from the multiplier synchronously with a clk with a ¼

phase difference from the clk, wherein the output from the delay is designated as a first output, and the output from the multiplier is designated as a second output.

24. The digital filter according to claim 15, wherein the second filter output unit is comprised of:

a multiplier for multiplying an output coefficient from the second coefficient update unit by the output data from the second data selection part; and

a delay for delaying the output data from the multiplier synchronously with a clk with a ¼

phase difference from the clk, wherein the output from the delay is designated as a third output, and the output from the multiplier is designated as a fourth output.