Parallel concatenated code with soft-in-soft-out interactive turbo decoder

• US 7,409,006 B2
• Filed: 07/05/2006
• Issued: 08/05/2008
• Est. Priority Date: 09/12/2000
• Status: Expired due to Fees

• Current Assignee: Broadcom Corporation (Broadcom, Inc.)
• Original Assignee: Broadcom Corporation (Broadcom, Inc.)
• Inventors: Shen, Ba-Zhong, Jones, Christopher R., Tran, Hau Thien, Cameron, Kelly Brian, Hughes, Thomas A. Jr.
• Primary Examiner(s): Wang; Ted
• Application Number:
  US11/481,365
• Publication Number:
  US 20060251184A1
• Time in Patent Office: 762 Days
• Field of Search: 375/295, 375/262, 375/265, 375/341, 714/701, 714/746, 714/755
• US Class Current: 375/295
• CPC Class Codes: H03M 13/151 using error location or error correction polynomials
• CPC Class Codes: H03M 13/1515 Reed-Solomon codes
• CPC Class Codes: H03M 13/25 Error detection or forward error correction by signal space coding, i.e. adding redundancy in the signal constellation, e.g. Trellis Coded Modulation [TCM] modulation codes H03M13/31
• CPC Class Codes: H03M 13/258 with turbo codes, e.g. Turbo Trellis Coded Modulation [TTCM]
• CPC Class Codes: H03M 13/27 using interleaving techniques
• CPC Class Codes: H03M 13/2757 Interleaver with an interleaving rule not provided for in the subgroups H03M13/2703 - H03M13/2753
• CPC Class Codes: H03M 13/29 combining two or more codes or code structures, e.g. product codes, generalised product codes, concatenated codes, inner and outer codes
• CPC Class Codes: H03M 13/2966 Turbo codes concatenated with another code, e.g. an outer block code
• CPC Class Codes: H03M 13/2978 Particular arrangement of the component decoders
• CPC Class Codes: H03M 13/3905 Maximum a posteriori probability [MAP] decoding or approximations thereof based on trellis or lattice decoding, e.g. forward-backward algorithm, log-MAP decoding, max-log-MAP decoding
• CPC Class Codes: H03M 13/3922 Add-Compare-Select [ACS] operation in forward or backward recursions
• CPC Class Codes: H03M 13/3927 Log-Likelihood Ratio [LLR] computation by combination of forward and backward metrics into LLRs
• CPC Class Codes: H03M 13/3972 using sliding window techniques or parallel windows
• CPC Class Codes: H03M 13/3988 for rate k/n convolutional codes, with k>1, obtained by convolutional encoders with k inputs and n outputs
• CPC Class Codes: H03M 13/4107 implementing add, compare, select [ACS] operations
• CPC Class Codes: H03M 13/6505 Memory efficient implementations
• CPC Class Codes: H03M 13/6561 Parallelized implementations
• CPC Class Codes: H04L 1/0041 Arrangements at the transmitter end
• CPC Class Codes: H04L 1/005 Iterative decoding, including iteration between signal detection and decoding operation
• CPC Class Codes: H04L 1/006 Trellis-coded modulation
• CPC Class Codes: H04L 1/0065 : Serial concatenated codes
• CPC Class Codes: H04L 1/0066 : Parallel concatenated codes
• CPC Class Codes: H04L 1/0068 : by puncturing
• CPC Class Codes: H04L 1/0071 : Use of interleaving interleaving per se H03M13/27

Abstract

A method for parallel concatenated (Turbo) encoding and decoding. Turbo encoders receive a sequence of input data tuples and encode them. The input sequence may correspond to a sequence of an original data source, or to an already coded data sequence such as provided by a Reed-Solomon encoder. A turbo encoder generally comprises two or more encoders separated by one or more interleavers. The input data tuples may be interleaved using a modulo scheme in which the interleaving is according to some method (such as block or random interleaving) with the added stipulation that the input tuples may be interleaved only to interleaved positions having the same modulo-N (where N is an integer) as they have in the input data sequence. If all the input tuples are encoded by all encoders then output tuples can be chosen sequentially from the encoders and no tuples will be missed. If the input tuples comprise multiple bits, the bits may be interleaved independently to interleaved positions having the same modulo-N and the same bit position. This may improve the robustness of the code. A first encoder may have no interleaver or all encoders may have interleavers, whether the input tuple bits are interleaved independently or not. Modulo type interleaving also allows decoding in parallel.

Claims

1. An apparatus, comprising:

a first constituent encoder that is operable to encode a plurality of information bits thereby generating a first plurality of encoded bits;

an interleaver that is operable to interleave the plurality of information bits thereby generating a plurality of interleaved bits;

a second constituent encoder that is operable to encode the plurality of interleaved bits thereby generating a second plurality of encoded bits;

a selector that is operable alternatively to select encoded bits from the first plurality of encoded bits and the second plurality of encoded bits thereby generating a symbol sequence that includes a first symbol that includes at least some encoded bits of the first plurality of encoded bits and a second symbol that includes at least some of the second plurality of encoded bits; and

a mapper that is operable to;

map the first symbol to a first constellation whose constellation points have a first mapping; and

map the second symbol to a second constellation whose constellation points have a second mapping; and

wherein;

the first constituent encoder encodes using a first code rate during a first time;

the second constituent encoder encodes using the first code rate during the first time;

the first constituent encoder encodes using a second code rate during a second time; and

the second constituent encoder encodes using the second code rate during the second time.

2. The apparatus of claim 1, wherein:

at least one symbol within the symbol sequence includes an uncoded bit.

3. The apparatus of claim 1, wherein:

the first symbol includes a first uncoded bit; and

the second symbol includes a second uncoded bit.

4. The apparatus of claim 1, wherein:

the first constellation include a first number of constellation points; and

the second constellation include a second number of constellation points.

5. The apparatus of claim 1, wherein:

the symbol sequence includes the first symbol, the second symbol, and a third symbol;

the first symbol includes a first uncoded bit;

the second symbol includes a second uncoded bit; and

the third symbol includes a third uncoded bit.

6. The apparatus of claim 1, further comprising:

a transmitter that is operable to process the mapped first symbol and the mapped second symbol thereby generating a transmit signal whose format comports with a communication channel; and

wherein;

the transmitter is operable to launch the transmit signal into the communication channel.

7. The apparatus of claim 1, further comprising:

a puncturing module that is operable to eliminate at least one encoded bit from at least one of the first plurality of encoded bits and the second plurality of encoded bits.

8. The apparatus of claim 1, wherein:

at least one interleaved bit of the plurality of interleaved bits is provided to the first constituent encoder.

9. The apparatus of claim 1, wherein:

at least one interleaved bit of the plurality of interleaved bits is provided to the first constituent encoder.

10. The apparatus of claim 1, wherein:

the second constituent encoder is operable to encode at least one information bit of the plurality of information bits.

11. The apparatus of claim 1, wherein:

the second constituent encoder is operable to encode at least one inverted information bit of the plurality of information bits.

12. The apparatus of claim 1, wherein:

the symbol sequence includes the first symbol, the second symbol, a third symbol, and a fourth symbol; and

the mapper that is operable to;

map the third symbol to the first constellation whose constellation points have the first mapping; and

map the fourth symbol to a third constellation whose constellation points have a third mapping.

13. The apparatus of claim 1, wherein:

a constant bit is provided to at least one of the first second constituent encoder and the second constituent encoder.

14. An apparatus, comprising:

a first constituent encoder that is operable to;

encode a first plurality of information bits thereby generating a first plurality of encoded bits; and

encode a second plurality of information bits thereby generating a second plurality of encoded bits;

an interleaver that is operable to;

interleave the first plurality of information bits thereby generating a first plurality of interleaved bits; and

interleave the second plurality of information bits thereby generating a second plurality of interleaved bits;

a second constituent encoder that is operable to;

encode the first plurality of interleaved bits thereby generating a third plurality of encoded bits; and

encode the second plurality of interleaved bits thereby generating a fourth plurality of encoded bits;

a puncturing module that is operable to eliminate at least one encoded bit from at least one of the first plurality of encoded bits, the second plurality of encoded bits, the third plurality of encoded bits, and the fourth plurality of encoded bits;

a selector that is operable alternatively to select encoded bits from the first plurality of encoded bits and the second plurality of encoded bits, after having undergone any puncturing by the puncturing module, thereby generating a symbol sequence that includes a first symbol that includes at least some encoded bits of the first plurality of encoded bits, a second symbol that includes at least some of the third plurality of encoded bits, a third symbol that includes at least some of the second plurality of encoded bits, and a fourth symbol that includes at least some of the fourth plurality of encoded bits; and

a mapper that is operable to;

map the first symbol to a first constellation whose constellation points have a first mapping;

map the second symbol to a second constellation whose constellation points have a second mapping;

map the third symbol to the first constellation whose constellation points have the first mapping; and

map the fourth symbol to a third constellation whose constellation points have a third mapping; and

wherein;

at least one symbol within the symbol sequence includes an uncoded bit;

the first constituent encoder encodes using a first code rate during a first time;

the second constituent encoder encodes using the first code rate during the first time;

the first constituent encoder encodes using a second code rate during a second time; and

the second constituent encoder encodes using the second code rate during the second time.

15. The apparatus of claim 14, wherein:

the first constellation include a first number of constellation points;

the second constellation include a second number of constellation points; and

at least one of the third constellation and the fourth constellation also includes the first number of constellation points.

16. The apparatus of claim 14, wherein:

a constant bit is provided to at least one of the first second constituent encoder and the second constituent encoder.

17. The apparatus of claim 14, further comprising:

a transmitter that is operable to process the mapped first symbol, the mapped second symbol, the mapped third symbol, and the mapped fourth symbol, thereby generating a transmit signal whose format comports with a communication channel; and

wherein;

the transmitter is operable to launch the transmit signal into the communication channel.

18. A method, comprising:

encoding a plurality of information bits using a first constituent encoder thereby generating a first plurality of encoded bits;

interleaving the plurality of information bits thereby generating a plurality of interleaved bits;

encoding the plurality of interleaved bits using a second constituent encoder thereby generating a second plurality of encoded bits;

alternatively selecting encoded bits from the first plurality of encoded bits and the second plurality of encoded bits thereby generating a symbol sequence that includes a first symbol that includes at least some encoded bits of the first plurality of encoded bits and a second symbol that includes at least some of the second plurality of encoded bits;

mapping the first symbol to a first constellation whose constellation points have a first mapping

mapping the second symbol to a second constellation whose constellation points have a second mapping;

operating the first constituent encoder using a first code rate during a first time;

operating the second constituent encoder using the first code rate during the first time;

operating the first constituent encoder using a second code rate during a second time; and

operating the second constituent encoder using the second code rate during the second time.

19. The method of claim 18, further comprising:

eliminating at least one encoded bit from at least one of the first plurality of encoded bits and the second plurality of encoded bits;

processing the mapped first symbol and the mapped second symbol thereby generating a transmit signal whose format comports with a communication channel; and

launching the transmit signal into the communication channel.

20. The method of claim 19, wherein:

providing at least one interleaved bit of the plurality of interleaved bits to the first constituent encoder;

or

encoding at least one inverted information bit of the plurality of information bits using the second constituent encoder.