Method and system for software debugging using a simulator

• US 7,409,330 B2
• Filed: 06/16/2005
• Issued: 08/05/2008
• Est. Priority Date: 06/16/2005
• Status: Expired due to Fees

• Current Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Kumamoto, Danny N.
• Primary Examiner(s): Rodriguez; Paul L
• Assistant Examiner(s): Thangavelu; Kandasamy
• Application Number:
  US11/154,315
• Publication Number:
  US 20070011656A1
• Time in Patent Office: 1,146 Days
• Field of Search: 703/22, 703/21, 703/17, 717/124, 717/128, 714/822, 714/38, 710/261, 712/233, 716/1
• US Class Current: 703/22
• CPC Class Codes: G06F 11/362 Software debugging
• CPC Class Codes: G06F 11/3664 Environments for testing or debugging software

Abstract

Systems and methods for debugging software and/or hardware are disclosed. A processor may execute a program for a certain amount of time. The context of the processor at the end of that time may then be made available to a simulator operable to simulate the processor. The program can then be executed from that point on the simulator using the context. Additionally, a context resulting from the execution of the program on the simulator may result and be restored to the processor for continued execution.

Claims

1. A method of debugging software, comprising:

executing a first software program on a first processor;

generating a first context during the execution of the first software program on the first processor wherein the first context comprises internal state of the first processor, first program and corresponding data, memory and registers;

stopping the first processor and storing the first context;

starting a first simulator process and providing the first context to the first simulator process, wherein the first simulator process executes on a second processor distinct from the first processor and the first simulator process is configured to simulate the first processor;

executing the first software program on the simulated first processor using the first context; and

debugging the first software program during the execution of the first software program on the simulated first processor.

2. The method of claim 1, wherein the first software program comprises a set of instructions, and wherein the set of instructions includes at least one instruction having a bug, and wherein first context is preserved prior to execution of the at least one instruction having a bug.

3. The method of claim 1, comprising

generating a second context in the first simulator process wherein the second context is the context of the processor being simulated and comprises internal state of the first processor, first program and corresponding data, memory and registers;

stopping the first simulator process on the second processor and storing the second context;

providing the second context to the first processor; and

executing the first software program on the first processor using the second context.

4. The method of claim 3, wherein the second context is generated by the first simulator process executing the first software program on the simulated first processor.

5. The method of claim 3, wherein the second context is the first context provided to the first simulator process to cause the first processor to execute the first software program from where it was previously stopped on the first processor.

6. The method of claim 3, further comprising:

executing a second software program on a third processor;

generating a third context during the execution of the second software program on the third processor wherein the third context comprises internal state of the third processor, second program and corresponding data, memory and registers;

stopping the third processor and storing the third context;

starting a second simulator process and providing the third context to the second simulator process, wherein the second simulator process executes on the second processor and the second simulator process is configured to simulate the third processor;

executing the first software program on the simulated first processor using the first context and the second software program on the simulated third processor using the third context; and

debugging the first software program during the execution of the first software program on the simulated first processor and debugging the second software program during the execution of the second software program on the simulated third processor.

7. The method of claim 6, wherein the third context is preserved prior to execution of the at least one instruction having a bug.

8. The method of claim 6, comprising

generating a fourth context in the second simulator process wherein the fourth context is the context of the third processor being simulated and comprises internal state of the third processor, second program and corresponding data, memory and registers;

stopping the second simulator process on the second processor and storing the fourth context;

providing the fourth context to the third processor; and

executing the second software program on the third processor using the fourth context.

9. The method of claim 1, further comprising providing a content of memory the first simulator process.

10. The method of claim 9, wherein said providing the content of memory comprises transferring control of memory from the first processor to the first simulator process.

11. The method of claim 9, wherein providing the content of memory comprises mapping the memory to the first simulator process.

12. A system for debugging software, said system comprising:

a first processor configured to

execute a first software program;

generate a first context during the execution of the first software program wherein the first context comprises internal state of the first processor, first program and corresponding data, memory and registers; and

stop the execution of the first software program, store the first context and provide the first context to a first simulator process; and

a second processor distinct from the first processor configured to;

start a first simulator process and receive the first context, wherein the first simulator process is configured to simulate the first processor;

execute the first software program on the simulated first processor using the first context; and

debug the first software program during the execution of the first software program on the simulated first processor.

13. The system of claim 12, wherein the first software program comprises a set of instructions, and wherein the set of instructions includes at least one instruction having a bug, and wherein the first processor is configured to preserve the first context prior to execution of the at least one instruction having a bug.

14. The system of claim 12, comprising:

the second processor is configured to;

generate a second context in the first simulator process wherein the second context is the context of the processor being simulated and comprises internal state of the first processor, first program and corresponding data, memory and registers;

stop the first simulator process and store the second context;

provide the second context to the first processor; and

the first processor is configured to execute the first software program using the second context.

15. The system of claim 14, the second context is generated by the first simulator process executing the first software program on the simulated first processor.

16. The system of claim 14, the second context is the first context provided to the first simulator process to cause the first processor to execute the first software program from where it was previously stopped on the first processor.

17. The system of claim 14, further comprising,

a third processor configured to:

execute a second software program;

generate a third context during the execution of the second software program wherein the third context comprises internal state of the third processor, second program and corresponding data, memory and registers;

stop the execution of the second software program, store the third context and provide the first context to a first simulator process; and

wherein the second processor is configured;

start a second simulator process and receive the third context, wherein the second simulator process is configured to simulate the third processor;

execute the first software program on the simulated first processor using the first context and the second software program on the simulated third processor using the third context; and

debug the first software program during the execution of the first software program on the simulated first processor and debug the second software program during the execution of the second software program on the simulated third processor.

18. The system of claim 17, wherein the third context is preserved prior to execution of the at least one instruction having a bug.

19. The system of claim 18, wherein the second processor is configured to:

generate a fourth context in the second simulator process wherein the fourth context is the context of the third processor being simulated and comprises internal state of the third processor, second program and corresponding data, memory and registers;

stop the second simulator process and store the fourth context;

provide the fourth context to the third processor; and

the third processor is configured to;

executing the second software program using the fourth context.

20. The system of claim 12, further comprising an operating system configured to provide a content of memory to the first simulator process.

21. The system of claim 20, wherein the operating system is configured to transfer control of memory to the first simulator process.

22. The system of claim 20, wherein the operating system is configured to map the memory to the first simulator process.

23. A method for debugging software comprising:

executing a first software program on a first processor;

generating a first context during the execution of the first software program on the first processor wherein the first context comprises internal state of the first processor, first program and corresponding data, memory and registers;

stopping the first processor and storing the first context;

starting a first simulator process and providing the first context to the first simulator process, wherein the first simulator process executes on a second processor distinct from the first processor and the first simulator process is configured to simulate the first processor;

executing the first software program on the simulated first processor using the first context;

debugging the first software program during the execution of the first software program on the simulated first processor;

generating a second context in the first simulator process wherein the second context is the context of the processor being simulated and comprises internal state of the first processor, first program and corresponding data, memory and registers;

stopping the first simulator process on the second processor and storing the second context;

providing the second context to the first processor; and

executing the first software program on the first processor using the second context.