Testing of integrated circuits

• US 7,409,612 B2
• Filed: 01/28/2004
• Issued: 08/05/2008
• Est. Priority Date: 02/10/2003
• Status: Active Grant

• Current Assignee: III Holdings 6, LLC
• Original Assignee: NXP B.V. (NXP Semiconductors NV)
• Inventors: Van De Logt, Leon Maria Albertus, Waayers, Thomas Franciscus, Van Der Heyden, Frank
• Primary Examiner(s): Britt; Cynthia
• Application Number:
  US10/545,121
• Publication Number:
  US 20060100810A1
• Time in Patent Office: 1,651 Days
• Field of Search: 714726-729
• US Class Current: 714/727
• CPC Class Codes: G01R 31/318536 Scan chain arrangements, e.g. connections, test bus, analog signals
• CPC Class Codes: G01R 31/318541 Scan latches or cell details

Abstract

An integrated circuit with a test interface contains a boundary scan chain with cells (14) coupled between a test data input (TDI) and output (TDO) in a shift register structure. Each cell (14) is also coupled between a respective one of the terminals (16) and the core circuit (10). A test control circuit (TAP_C) supports an instruction to switch the boundary scan chain to a mode in which mode selectable first ones of the cells (14) transport data serially along the boundary scan chain while selectable second ones of the cells (14) write or read data that has been or will be transported through the first ones of the cells (14) in the further mode to or from the terminals (16) from or to the scan chain.

Claims

1. An integrated circuit comprising:

a core circuit;

terminals for coupling the core circuit to circuitry external to the integrated circuit,

a test data input and a test data output;

a boundary scan chain comprising cells coupled between the test data input and output in a shift register structure, each cell also coupled between a respective one of the terminals and the core circuit,

a test control circuit arranged to switch the boundary scan chain between a functional mode, in which the cells permit signal flow between the terminals and the core circuit, and a test mode, in which test data is shifted serially through the cells along the boundary scan chain and in which the cells intercept signal flow between the respective ones of the terminals and the core circuit,

wherein the test control circuit is arranged to execute an instruction to switch the boundary scan chain to a further mode, in which further mode selectable first ones of the cells transport data serially along the boundary scan chain while selectable second ones of the cells write or read data that has been or will be transported through the first ones of the cells in the further mode to or from the terminals from or to the scan chain.

2. An integrated circuit according to claim 1, comprising configuration cells for respective cells of the boundary scan chain, the configuration cells being loadable with configuration data from the test data input, each cell of the boundary scan chain having a configuration input coupled to its configuration cell for selecting whether the cell of the boundary scan chain has to function as one of the first ones or one of the second ones of the cells under the control of the configuration data.

3. An integrated circuit according to claim 2, wherein each of the cells of the boundary scan chain comprises a scan flip-flop and an update flip-flop, the scan flip-flops of successive cells in the boundary scan chain being coupled serially to form the shift register structure, the update flip-flop of the cell being coupled to the shift register structure to receive test data from the scan flip-flop, the update flip-flop supplying the test data to the respective one of the terminals to which the cell is coupled in the test mode, and wherein the update flip-flop of at least part of the cells function as said configuration cells to supply configuration data in the further mode.

4. An integrated circuit according to claim 3, each cell of the boundary scan chain comprising a multiplexing circuit with inputs coupled to the shift register structure and to the core circuit, an output coupled to the terminal for the cell, and a control input coupled to the test control circuit and to an output of the update flip-flop of the cell, so that in the further mode the multiplexing circuit couples the core circuit to the terminal when the update flip-flop indicates that the cell is a first one of the cells and the multiplexing circuit couples the shift register structure to the terminal when the update flip-flop indicates that the cell is a second one of the cells.

5. An integrated circuit according to claim 1, wherein each cell comprises:

a scan input (SI) and a scan output, the test data input being coupled to the scan input (SI) of a frontmost one of the cells in the boundary scan chain, each further one of the cells having its scan input coupled to the scan output of a preceding one of the cells, and a final one of the cells having its scan output (SO) coupled to the test data output;

a scan flip-flop having an input coupled to the scan input (SI) of the cell;

a multiplexing circuit comprising inputs coupled to the scan input of the cell and to an output of the scan flip-flop, the multiplexing circuit having an output coupled to the scan output of the cell and to a control input;

a configuration input coupled to the control input of the multiplexing circuit for selecting that the multiplexing circuit couples the scan input to the scan output in the further mode if the cell is selected to be a first one of the cells.

6. An integrated circuit according to claim 5, wherein each cell has a functional input coupled to an input of the scan flip-flop, at least part of the cells being input cells, the multiplexing circuit of each input cell comprising a further input coupled to the functional input, the multiplexing circuit being arranged to couple the functional input to the scan outputs in the input cells in the further mode if the input cell is selected to be a second one of the cells.

7. An integrated circuit according to claim 5, wherein each cell has a functional input coupled to an input of the scan flip-flop, at least part of the cells being input cells, the multiplexing circuit of each input cell comprising a further input coupled to the functional input, the multiplexing circuit being arranged to couple the functional input to an input of the scan flip-flop and an output of the scan flip-flop to the scan output in the further mode if the cell is selected to be a second one of the cells.

8. An integrated circuit according to claim 5, wherein each cell has a functional output, and wherein at least part of the cells are output cells, the multiplexing circuit of each output cell being arranged to couple the functional output to the scan output in the output ones of the cells in the further mode if the output cell is selected to be a second one of the cells.

9. An integrated circuit according to claim 5, wherein each cell has a functional output, at least part of the cells being output cells, comprising an output circuit coupled between the scan flip-flop and the functional output, the output circuit of each output cell being arranged to output data received from the shift register structure at the functional output in the further mode if the cell is selected to be a second one of the cells and to prevent data from the shift register structure from being output at the functional output in the further mode if the cell is selected to be a first one of the cells.

10. An integrated circuit according to claim 9, wherein each cell comprises an update flip-flop coupled between the shift register structure and the output circuit, the output circuit outputting data signals latched into the update flip-flop from the update flip-flop to the functional output in the further mode if the cell is selected to be a second one of the cells.

11. An integrated circuit according to claim 9, wherein the output circuit outputs data signals continuously from the shift register structure to the functional output in the further mode if the cell is selected to be a second one of the cells.

12. An integrated circuit according to claim 9, wherein the output circuit of each output cell has a multiplexing function and multiplex inputs are coupled to the functional input of the cell and to the shift register structure, the output circuit coupling the functional input to the functional output in the further mode if the cell is selected to be a first one of the cells.

13. An integrated circuit according to claim 1, wherein each cell comprises a scan flip-flop, the scan flip-flops of successive cells in the boundary scan chain being coupled in series in the shift register structure, the control circuit supporting an instruction for switching the integrated circuit to asynchronous operation in said further mode, the first ones of the cells creating a transparent path bypassing the scan flip-flops of the first ones of the cells in the shift register structure in asynchronous operation, such that data are being directly written or read to or from the terminals from or to the shift register structure in the second ones of the cells in asynchronous operation.

14. An integrated circuit according to claim 13, the control circuit supporting a further instruction for switching the integrated circuit to synchronous operation in said further mode, a length of the boundary scan chain being adapted in that the first ones of the cells are made transparent along the shift register structure in the synchronous mode.

15. An integrated circuit according to claim 1, wherein each cell comprises a scan flip-flop, the scan flip-flops of successive cells in the boundary scan chain being coupled in series in the shift register structure, the control circuit supporting an instruction for switching the integrated circuit to synchronous operation in said further mode, a length of the boundary scan chain being adapted in that the first ones of the cells are made transparent in the shift register structure in the synchronous mode.

16. An integrated circuit according to claim 1, wherein the control circuit comprises a state machine defining a plurality of states which the state machine assumes under the control of a test protocol in the test mode and which determine control signals issued to control inputs of the cells for controlling the cells, said test protocol being used to control the state machine also in the further mode, each cell having further control inputs for receiving a control signal that indicates whether the integrated circuit operates in the further mode and a configuration signal that distinguishes whether cells function as a first one of the cells or a second one of the cells, for controlling the cell with the control signals issued to the inputs in combination with the control signal and the configuration signal.

17. An integrated circuit according to claim 16, wherein the states include a shift state in which the control circuit controls the cells to shift data through the shift register structure in the test mode, the cells being arranged such that the second ones of the cells transport the data that has been or will be transported through the first ones of the cells in the shift state between the scan chain and the terminals or the core circuit when the state machine is in the shift state.

18. An electronic circuit, comprising an integrated circuit according to claim 1 and one or more further integrated circuits coupled to the terminals of the integrated circuit, wherein test inputs and outputs of the integrated circuits are coupled in a daisy chain, and test control inputs of the integrated circuits are coupled in parallel.

19. A method of operating an electronic circuit that comprises an integrated circuit and a further circuit coupled to each other, the integrated circuit comprising a boundary scan chain with cells coupled between a test data input and output of the integrated circuit in a shift register structure, each cell being also coupled between a respective one of terminals of the integrated circuit and a core circuit of the integrated circuit, the integrated circuit being switchable

to a functional mode, in which the cells permit signal flow between the terminals and the core circuit,

to a test mode, in which test data is shifted serially through the cells along the boundary scan chain and in which the cells intercept signal flow between the respective ones of the terminals and the core circuit, and

upon an instruction, to a further mode in which selectable first ones of the cells transport data serially along the boundary scan chain while selectable second ones of the cells write or read data that has been or will be transported through the first ones of the cells in the further mode to or from the terminals from or to the scan chain, wherein the method comprises a step of:

switching the integrated circuit to the further mode and supplying and/or extracting successive signals to and/or from selected ones of the terminals through the boundary scan chain, while not transporting signals through the scan chain for or from other ones of the terminals intervening between the successive signals.

20. A method according to claim 19, wherein a particular one of the cells is configured to be a second one of the cells, all other cells that precede said particular one of the cells along the boundary scan chain from the test data input being configured to be first ones of the cells.

21. A method according to claim 19, wherein a particular one of the cells is configured to be a second one of the cells, all other cells that succeed said particular one of the cells along the boundary scan chain to the test data output being configured to be first ones of the cells (14).

22. A method according to claim 19, wherein an input one of the cells and an output one of the cells that succeeds the input one of the cells directly or indirectly along the boundary scan chain are configured to be second ones of the cells, any intervening cells between the input one of the cells and the output one of the cells all being configured to be first ones of the cells.

23. A method according to claim 19, comprising a bypassing of the cells coupled to said other ones of the terminals in the scan chain and supplying the successive signals asynchronously from a clock for serial transport through the shift register structure.