System and method of reading non-volatile computer memory

• US 7,409,623 B2
• Filed: 11/04/2004
• Issued: 08/05/2008
• Est. Priority Date: 11/04/2004
• Status: Expired due to Fees

• Current Assignee: Progressive Semiconductor Solutions LLC (Acacia Research Corporation)
• Original Assignee: SigmaTel Incorporated (NXP Semiconductors NV)
• Inventors: Baker, David Cureton, Abbott, Grayson Dale, Zeevi, Josef
• Primary Examiner(s): Chase; Shelly
• Assistant Examiner(s): RIZK, SAMIR WADIE
• Application Number:
  US10/981,086
• Publication Number:
  US 20060107130A1
• Time in Patent Office: 1,370 Days
• Field of Search: 711/168, 711/163
• US Class Current: 714/763
• CPC Class Codes: G06F 11/1004 to protect a block of data words, e.g. CRC or checksum G06F11/1076 takes precedence; security arrangements for protecting computers or computer systems against unauthorized activity G06F21/00

Abstract

The disclosure is directed to a method of reading a portion of a non-volatile computer memory including reading a first portion of a redundant memory area of a data sector of the non-volatile computer memory. The first portion of the redundant memory area includes data associated with the data sector. The first portion of the redundant memory area includes a cyclic redundancy check code.

Claims

1. A method of reading a portion of a non-volatile computer memory, the method comprising:

reading a first portion of a redundant memory area of a data sector of a non-volatile computer memory, the first portion of the redundant memory area including data associated with the data sector;

wherein the first portion of the redundant memory area includes a cyclic redundancy check code;

evaluating the cyclic redundancy check code to detect a memory error with respect to the first portion, wherein an overwrite flags include a block status flag, a page status flag and an update status flag in the redundant memory area is checked by the cyclic redundancy check code;

reading a second portion of the redundant memory area in response to detection of the memory error; and

wherein the non-volatile computer memory comprises a multi-level cell flash memory device.

2. The method of claim 1, wherein the second portion of the redundant memory area includes an error correction code.

3. The method of claim 1, further comprising reading the data sector after detecting the memory error and executing an error correction routine in response to detecting the memory error.

4. The method of claim 3, wherein reading the second portion of the redundant memory area comprises reading an error correction code from the second portion of the redundant memory area prior to executing the error correction routine.

5. The method of claim 1, further comprising generating a memory sector layout table based on that data included within the first portion of the redundant memory area.

6. The method of claim 5, wherein the memory sector layout table is stored in a random access memory device.

7. The method of claim 1, further comprising building a map of bad sectors based on the data included within the first portion of the redundant memory area.

8. The method of claim 1, further comprising identifying a type of data stored in a sector based on that data included within the first portion of the redundant memory area.

9. The method of claim 1, further comprising checking the value of a security code based on that data included within the first portion of the redundant memory area.

10. The method of claim 1, wherein the first portion of the redundant memory area includes data selected from a group consisting of overwrite flags, logical address data, format reserve data, security codes, data management flags, and tags identifying the kind of data in the sector, and wherein the overwrite flags include a block status flag, a page status flag, and an update status flag.

11. The method of claim 1, wherein the redundant memory area is sixteen bytes and wherein the first portion of the redundant memory area is seven bytes.

12. The method of claim 1, wherein the redundant memory area is sixty four bytes and wherein the first portion of the redundant memory area is twenty eight bytes.

13. The method of claim 1, wherein the time to read the first portion of the redundant memory area and to evaluate the cyclic redundancy check is less than the time to read the data sector and to perform an error correction code operation using the error correction code.

14. A method of reading a non-volatile computer memory, the method comprising:

reading a first portion of a first redundant memory area of a first data sector of a non-volatile computer memory, the first redundant memory area including data associated with the first data sector, the first portion of the first redundant memory area including a first cyclic redundancy check code associated with the first portion of the first redundant memory area;

evaluating the first cyclic redundancy check code to determine whether noise or errors exist in an overwrite flags include a block status flag, a page status flag and an update status flag present in the first portion of the first redundant memory area;

reading a first portion of a second redundant memory area of a second data sector of the non-volatile computer memory, the second redundant memory area including data associated with the second data sector, the first portion of the second redundant memory area including a second cyclic redundancy check code; and

wherein the non-volatile computer memory comprises a multi-level cell flash memory device.

15. The method of claim 14, wherein the first redundant memory area includes a first error correction code stored in a second portion of the first redundant memory area, and wherein the second redundant memory area includes a second error correction code stored in a second portion of the second redundant memory area.

16. The method of claim 15, further comprising evaluating the first cyclic redundancy check code to determine whether a memory error is detected with respect to the first portion of the first redundant memory area, and evaluating the second cyclic redundancy check code to determine whether a memory error is detected with respect to the first portion of the second redundant memory area.

17. The method of claim 14, wherein the data associated with the first data sector and the data associated with the second data sector include data selected from a group consisting of logical address data, format reserve data, and data management flags.

18. The method of claim 14, wherein the non-volatile memory includes a plurality of blocks, a first of the plurality of blocks including the first data sector and a second plurality of blocks including the second data sector.

19. The method of claim 14, wherein the first redundant memory area and the second redundant memory area include system data and wherein the first data sector and the second data sector further include user data.

20. A non-volatile computer memory device comprising:

a multi-level cell flash memory device comprising;

a first memory element including a first user data and a first redundant memory, the first redundant memory including a first portion and a second portion, the first portion of the first redundant memory including a first cyclic redundancy check code and the second portion of the first redundant memory including a first error correction code, wherein the first cyclic redundancy check code is associated with error detection of data stored in the first portion of the first redundant memory, wherein an overwrite flags include a block status flag, a page status flag and an update status flag is present in the first portion of the first redundant memory, and wherein the first cyclic redundancy check code is configured to check the overwrite flag; and

a second memory element including a second user data and a second redundant memory, the second redundant memory including a first portion and a second portion, the first portion of the second redundant memory including a second cyclic redundancy check code and the second portion of the second redundant memory including a second error correction code.

21. The non-volatile computer memory device of claim 20, wherein the first error correction code is associated with error correction of data stored in the first user data and in the first redundant memory.

22. A system comprising:

a processor;

a dynamic memory accessible to the processor; and

a non-volatile memory comprising a multi-level cell flash memory device accessible to the processor, the non-volatile memory comprising;

a first memory element including a first user data and a first redundant memory, the first redundant memory including a first portion and a second portion, the first portion of the first redundant memory including a first cyclic redundancy check code and the second portion of the first redundant memory including a first error correction code, wherein an overwrite flags include a block status flag, a page status flag and an update status flag is present in the first redundant memory that is capable of being checked by the first cyclic redundancy check code; and

a second memory element including a second user data and a second redundant memory, the second redundant memory including a first portion and a second portion, the first portion of the second redundant memory including a second cyclic redundancy check code and the second portion of the second redundant memory including a second error correction code.

23. The system of claim 22, wherein the dynamic memory includes data that represents a map of a region of the non-volatile memory, the region of the non-volatile memory including the first memory element and the second memory element.

24. The system of claim 23, wherein the dynamic memory includes mapping program logic executable by the processor to generate the data that represents the map of the region of the non-volatile memory and wherein the map is generated in response to reading the first portion of the first redundant memory and in response to reading the first portion of the second redundant memory, and without reading the first user data and without reading the second user data.

25. The system of claim 22, wherein the dynamic memory includes program logic executable by the processor to evaluate the first cyclic redundancy check code to detect an error within the first memory element, and wherein the dynamic memory further includes program logic executable by the processor to correct the error within the first memory element using the first error correction code.