Efficient design to implement LDPC (Low Density Parity Check) decoder
First Claim
1. A decoder that is operable to decode an LDPC (Low Density Parity Check) coded signal, the decoder comprising:
- a metric generator that is operable to;
receive first I, Q (In-phase, Quadrature) values corresponding to a first symbol of the LDPC coded signal and is operable to generate a first plurality of bit metrics there from;
receive second I, Q values corresponding to a second symbol of the LDPC coded signal and is operable to generate a second plurality of bit metrics there from;
a metric memory that is operable to;
store the first plurality of bit metrics and the second plurality of bit metrics;
support dual port memory management thereby outputting the first plurality of bit metrics while receiving the second plurality of bit metrics from the metric generator;
support dual port memory management thereby outputting the second plurality of bit metrics while receiving a third plurality of bit metrics from the metric generator;
a plurality of bit/check processors that is operable to;
successively receive the first plurality of bit metrics, the second plurality of bit metrics, and the third plurality of bit metrics;
perform both bit node processing that involves updating a plurality of edge messages with respect to a plurality of bit nodes and check node processing that involves updating a plurality of edge messages with respect to a plurality of check nodes;
a message passing memory that is operable to;
store the plurality of edge messages with respect to the plurality of bit nodes after undergoing bit node processing within the plurality of bit/check processors;
store the plurality of edge messages with respect to the plurality of check nodes after undergoing check node processing within the plurality of bit/check processors;
a barrel shifter that is operable to;
shift the plurality of edge messages with respect to the plurality of bit nodes that is accessed from the memory passing memory;
provide the shifted plurality of edge messages with respect to the plurality of bit nodes to the plurality of bit/check processors for subsequent check node processing;
shift the plurality of edge messages with respect to the plurality of check nodes that is accessed from the memory passing memory; and
provide the shifted plurality of edge messages with respect to the plurality of check nodes to the plurality of bit/check processors for subsequent bit node processing.
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Abstract
Efficient design to implement LDPC decoder. The efficient design presented herein provides for a solution that is much easier, smaller, and has less complexity than other possible solutions. The use of a ping-pong memory structure (or pseudo-dual port memory structure) in conjunction with a metric generator near the decoder'"'"'s front end allows parallel bit/check node processing. An intelligently operating barrel shifter operates with a message passing memory that is operable to store updated edges messages with respect to check nodes as well as updated edges messages with respect to bit nodes. Using an efficient addressing scheme allows the same memory structure to store the two types of edges messages with respect to bit nodes: (1) corresponding to information bits and (2) corresponding to parity bits. In addition, an intelligently designed hardware macro block may be instantiated a number of times into the decoder design to support ever greater design efficiency.
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Citations
37 Claims
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1. A decoder that is operable to decode an LDPC (Low Density Parity Check) coded signal, the decoder comprising:
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a metric generator that is operable to; receive first I, Q (In-phase, Quadrature) values corresponding to a first symbol of the LDPC coded signal and is operable to generate a first plurality of bit metrics there from; receive second I, Q values corresponding to a second symbol of the LDPC coded signal and is operable to generate a second plurality of bit metrics there from; a metric memory that is operable to; store the first plurality of bit metrics and the second plurality of bit metrics; support dual port memory management thereby outputting the first plurality of bit metrics while receiving the second plurality of bit metrics from the metric generator; support dual port memory management thereby outputting the second plurality of bit metrics while receiving a third plurality of bit metrics from the metric generator; a plurality of bit/check processors that is operable to; successively receive the first plurality of bit metrics, the second plurality of bit metrics, and the third plurality of bit metrics; perform both bit node processing that involves updating a plurality of edge messages with respect to a plurality of bit nodes and check node processing that involves updating a plurality of edge messages with respect to a plurality of check nodes; a message passing memory that is operable to; store the plurality of edge messages with respect to the plurality of bit nodes after undergoing bit node processing within the plurality of bit/check processors; store the plurality of edge messages with respect to the plurality of check nodes after undergoing check node processing within the plurality of bit/check processors; a barrel shifter that is operable to; shift the plurality of edge messages with respect to the plurality of bit nodes that is accessed from the memory passing memory; provide the shifted plurality of edge messages with respect to the plurality of bit nodes to the plurality of bit/check processors for subsequent check node processing; shift the plurality of edge messages with respect to the plurality of check nodes that is accessed from the memory passing memory; and provide the shifted plurality of edge messages with respect to the plurality of check nodes to the plurality of bit/check processors for subsequent bit node processing. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13)
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14. A decoder that is operable to decode an LDPC (Low Density Parity Check) coded signal, the decoder comprising:
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a plurality of bit/check processors that is operable to; receive a plurality of bit metrics; perform both bit node processing that involves updating a plurality of edge messages with respect to a plurality of bit nodes and check node processing that involves updating a plurality of edge messages with respect to a plurality of check nodes; a message passing memory that is operable to; store the plurality of edge messages with respect to the plurality of bit nodes after undergoing bit node processing within the plurality of bit/check processors; store the plurality of edge messages with respect to the plurality of check nodes after undergoing check node processing within the plurality of bit/check processors; a barrel shifter that is operable to; shift the plurality of edge messages with respect to the plurality of bit nodes that is accessed from the memory passing memory; provide the shifted plurality of edge messages with respect to the plurality of bit nodes to the plurality of bit/check processors for subsequent check node processing; shift the plurality of edge messages with respect to the plurality of check nodes that is accessed from the memory passing memory; and provide the shifted plurality of edge messages with respect to the plurality of check nodes to the plurality of bit/check processors for subsequent bit node processing. - View Dependent Claims (15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27)
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28. A method for decoding an LDPC (Low Density Parity Check) coded signal, the method comprising:
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receiving first I, Q (In-phase, Quadrature) values corresponding to a first symbol of the LDPC coded signal and generating a first plurality of bit metrics there from; receiving second I, Q values corresponding to a second symbol of the LDPC coded signal and generating a second plurality of bit metrics there from; storing the first plurality of bit metrics and the second plurality of bit metrics; supporting dual port memory management thereby outputting the first plurality of bit metrics while receiving the second plurality of bit metrics; supporting dual port memory management thereby outputting the second plurality of bit metrics while receiving a third plurality of bit metrics; successively receiving the first plurality of bit metrics, the second plurality of bit metrics, and the third plurality of bit metrics; performing both bit node processing that involves updating a plurality of edge messages with respect to a plurality of bit nodes and check node processing that involves updating a plurality of edge messages with respect to a plurality of check nodes; storing the plurality of edge messages with respect to the plurality of bit nodes after undergoing bit node processing; storing the plurality of edge messages with respect to the plurality of check nodes after undergoing check node processing; shifting the plurality of edge messages with respect to the plurality of bit nodes into an appropriate arrangement for subsequent check node processing; and shifting the plurality of edge messages with respect to the plurality of check nodes into an appropriate arrangement for subsequent bit node processing. - View Dependent Claims (29, 30, 31, 32, 33, 34, 35, 36, 37)
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Specification