Architecture and interconnect scheme for programmable logic circuits

• US 7,409,664 B2
• Filed: 12/09/2005
• Issued: 08/05/2008
• Est. Priority Date: 08/03/1993
• Status: Expired due to Fees

• Current Assignee: Actel Corporation (Microchip Technology Incorporated)
• Original Assignee: Actel Corporation (Microchip Technology Incorporated)
• Inventors: Ting, Benjamin S.
• Primary Examiner(s): Lin; Sun J
• Application Number:
  US11/299,248
• Publication Number:
  US 20060095886A1
• Time in Patent Office: 970 Days
• Field of Search: 716/12, 716/14, 716/16, 716/17, 326/38, 326/41
• US Class Current: 326/41
• CPC Class Codes: H03K 19/17704 the logic functions being realised by the interconnection of rows and columns
• CPC Class Codes: H03K 19/17728 Reconfigurable logic blocks, e.g. lookup tables
• CPC Class Codes: H03K 19/17736 Structural details of routing resources
• CPC Class Codes: H03K 19/1778 Structural details for adapting physical parameters
• CPC Class Codes: H03K 19/17796 for physical disposition of blocks

Abstract

An architecture of hierarchical interconnect scheme for field programmable gate arrays (FPGAs). A first layer of routing network lines is used to provide connections amongst sets of block connectors where block connectors are used to provide connectability between logical cells and accessibility to the hierarchical routing network. A second layer of routing network lines provides connectability between different first layers of routing network lines. Additional layers of routing network lines are implemented to provide connectability between different prior layers of routing network lines. An additional routing layer is added when the number of cells is increased as the prior cell count in the array increases while the length of the routing lines and the number of routing lines also increases. Switching networks are used to provide connectability among same and different layers of routing network lines, each switching network composed primarily of program controlled passgates and, when needed, drivers.

Claims

1. An integrated circuit, comprising:

a first region comprising;

a first plurality of cells located along a first dimension and a second dimension, wherein the first region has a first span along the first dimension and a second span along the second dimension;

a plurality of switches; and

a first plurality of conductors located within the first region, wherein each conductor of the first plurality of conductors to selectively couple to inputs and outputs of cells of the first plurality of cells and conductors of the first plurality of conductors through the plurality of switches and wherein the first plurality of conductors span cells of the first plurality of cells along the first dimension and the second dimension, wherein the first plurality of conductors comprises;

a first conductor having a first span along the first dimension;

a second conductor having a second span along the first dimension;

a third conductor having a third span along the second dimension; and

a fourth conductor having a fourth span along the second dimension;

wherein the first span of the first region is greater than the first span of the first conductor and the first span of the first conductor is greater than the second span of the second conductor,

wherein the second span of the first region is greater than the third span of the third conductor and the third span of the third conductor is greater than the fourth span of the fourth conductor;

a second region located within the first region, having a span along the first dimension, comprising;

a subgroup of cells of the first plurality of cells located in the second region, wherein the span of the second region is less than the second span of the second conductor;

a fifth conductor of the first plurality of conductors located within the second region having a fifth span equal to the span of the second region along the first dimension; and

a first cell of the first plurality of cells;

a second cell of the first plurality of cells; and

two independently program controlled switches comprising a first switch and a second switch, wherein the first cell is configured to selectively couple to drive the fifth conductor through at least the first switch and wherein the second cell is configured to selectively couple to drive the fifth conductor through at least the second switch.

2. The integrated circuit as set forth in claim 1, further comprising a third region, located within the first region, comprising a plurality of replicated second regions having at least a two by two arrangement along the first dimension and the second dimension, wherein the second conductor and the fourth conductor are located in the third region, wherein the second span of the second conductor is equal to span of the third region along the first dimension and wherein the fourth span of the fourth conductor is equal to a span of the third region along the second dimension.

3. The integrated circuit as set forth in claim 2, wherein the first region further comprises a fourth region comprising a plurality of replicated third regions having at least a two by two arrangements along the first dimension and the second dimension, wherein the first span of the first conductor is equal to a span of the fourth region along the first dimension and the third span of the third conductor is equal to a span of the fourth region along the second dimension and wherein the first conductor and the third conductor are located in the fourth region.

4. The integrated circuit as set forth in claim 3, wherein the first region further comprises:

a third switch, wherein the first conductor is configured to selectively couple to the third conductor through at least the third switch; and

a fourth switch, wherein the second conductor is configured to selectively couple to the fourth conductor through at least the fourth switch.

5. The integrated circuit as set forth in claim 4, wherein the first region further comprises:

a sixth conductor of the first plurality of conductors having a sixth span being greater than the first span of the first conductor and lesser than the first span of the first region along the first dimension;

a seventh conductor of the first plurality of conductors having a seventh span being greater than the third span of the third conductor and lesser than the second span of the first region along the second dimension; and

a fifth switch, wherein the sixth conductor is configured to selectively couple to the seventh conductor through at least the fifth switch.

6. The integrated circuit as set forth in claim 4, wherein in the first region,

the first conductor is configured to selectively couple to the third conductor through the third switch without requiring selectable connection through another conductor;

and

the second conductor is configured to selectively couple to the fourth conductor through the fourth switch without requiring selectable connection through another conductor.

7. The integrated circuit as set forth in claim 5, wherein in the first region,

the first conductor is configured to selectively couple to the third conductor through the third switch without requiring selectable connection through another conductor;

the second conductor is configured to selectively couple to the fourth conductor through the fourth switch without requiring selectable connection through another conductor; and

the sixth conductor is configured to selectively couple to the seventh conductor through the fifth switch without requiring selectable connection through another conductor.

8. The integrated circuit as set forth in claim 3, wherein the first region further comprises a third switch, and the first conductor is configured to selectively couple to and drive the second conductor through at least the third switch.

9. The integrated circuit as set forth in claim 8, wherein the first region further comprising a fourth switch, wherein the third conductor is configured to selectively couple to and drive the fourth conductor through at least the fourth switch.

10. The integrated circuit as set forth in claim 9, wherein the first region further comprises:

a sixth conductor of the first plurality of conductors having a sixth span being greater than the first span of the first conductor and lesser than the first span of the first region along the first dimension; and

a fifth switch, wherein the sixth conductor is configured to selectively couple to and drive the first conductor through at least the fifth switch.

11. The integrated circuit as set forth in claim 9, wherein in the first region,

the first conductor is configured to selectively couple to and drive the second conductor through the third switch without requiring selectable connection through another conductor;

and

the third conductor is configured to selectively couple to and drive the fourth conductor through the fourth switch without requiring selectable connection through another conductor.

12. The integrated circuit as set forth in claim 10, wherein the first region further comprises:

a seventh conductor of the first plurality of conductors having a seventh span being greater than the third span of the third conductor and lesser than the second span of the first region along the second dimension; and

a sixth switch, wherein the seventh conductor is configured to selectively couple to and drive the third conductor through at least the sixth switch.

13. The integrated circuit as set forth in claim 10, wherein in the first region,

the first conductor is configured to selectively couple to and drive the second conductor through the third switch without requiring selectable connection through another conductor;

the third conductor is configured to selectively couple to and drive the fourth conductor through the fourth switch without requiring selectable connection through another conductor; and

the sixth conductor is configured to selectively couple to and drive the first conductor through the fifth switch without requiring selectable connection through another conductor.

14. The integrated circuit as set forth in claim 12, wherein in the first region,

the first conductor is configured to selectively couple to and drive the second conductor through the third switch without requiring selectable connection through another conductor;

the third conductor is configured to selectively couple to and drive the fourth conductor through the fourth switch without requiring selectable connection through another conductor;

the sixth conductor is configured to selectively couple to and drive the first conductor through the fifth switch without requiring selectable connection through another conductor; and

the seventh conductor is configured to selectively couple to and drive the third conductor through the sixth switch without requiring selectable connection through another conductor.

15. The integrated circuit as set forth in claim 1, wherein the first region further comprises:

a sixth conductor of the first plurality of conductors having a sixth span being greater than the first span of the first conductor and lesser than the first span of the first region along the first dimension; and

a seventh conductor of the first plurality of conductors having a seventh span being greater than the third span of the third conductor and lesser than the second span of the first region along the second dimension.

16. A method of operating an integrated circuit, comprising:

providing a first region comprising a first plurality of cells located along a first dimension and a second dimension, wherein each of the first plurality of cells has an input and an output, and wherein the first region has a first span along the first dimension and a second span along the second dimension;

providing a plurality of switches in the first region;

providing a first plurality of conductors located within the first region, wherein the first plurality of conductors comprises a first conductor having a first span along the first dimension, a second conductor having a second span along the first dimension, a third conductor having a third span along the second dimension and a fourth conductor having a fourth span along the second dimension;

selectively coupling each of the first plurality of conductors to the inputs and outputs of cells of the first plurality of cells and conductors of the first plurality of conductors through switches;

wherein the first span of the first region is greater than the first span of the first conductor and the first span of the first conductor is greater than the second span of the second conductor;

wherein the second span of the first region is greater than the third span of the third conductor and the third span of the third conductor is greater than the fourth span of the fourth conductor;

providing a second region, located within the first region, having a span along the first dimension, comprising a subgroup of cells of the first plurality of cells, wherein the span of the second region is less than the second span of the second conductor along the first dimension;

providing a fifth conductor of the first plurality of conductors in the second region having a fifth span equal to the span of the second region along the first dimension;

providing a first cell and a second cell of the first plurality of cells and two independently program controlled first switch and second switch in the first region;

selectively coupling the first cell to drive the fifth conductor through at least the first switch; and

selectively coupling the second cell to drive the fifth conductor through at least the second switch.

17. The method as set forth in claim 16, further comprising providing a third region, located within the first region, comprising a plurality of replicated second regions having at least a two by two arrangements along the first dimension and the second dimension, wherein the second span of the second conductor is equal to a span of the third region along the first dimension and the fourth span of the fourth conductor is equal to a span of the third region along the second dimension and wherein the second conductor and the fourth conductor are located in the third region.

18. The method as set forth in claim 17, further comprising providing a fourth region, located within the first region, comprising a plurality of replicated third regions having at least a two by two arrangements along the first dimension and the second dimension, wherein the first span of the first conductor is equal to a span of the fourth region along the first dimension and the third span of the third conductor is equal to a span of the fourth region along the second dimension and wherein the first conductor and the third conductor are located in the fourth region.

19. The method as set forth in claim 18, further comprising:

providing a third switch in the first region;

selectively coupling the first conductor to the third conductor through at least the third switch;

providing a fourth switch in the first region; and

selectively coupling the second conductor to the fourth conductor through at least the fourth switch.

20. The method as set forth in claim 19, further comprising:

providing a sixth conductor of the first plurality of conductors in the first region having a greater span than the first span of the first conductor and a lesser span than the first span of the first region along the first dimension;

providing a seventh conductor of the first plurality of conductors in the first region having a span greater than the third span of the third conductor and a lesser span than the second span of the first region along the second dimension;

providing a fifth switch in the first region; and

selectively coupling the sixth conductor to the seventh conductor through at least the fifth switch.

21. The method as set forth in claim 19, further comprising:

selectively coupling the first conductor to the third conductor through the third switch without requiring selectable connection through another conductor; and

selectively coupling the second conductor to the fourth conductor through the fourth switch without requiring selectable connection through another conductor.

22. The method as set forth in claim 20, further comprising:

selectively coupling the first conductor to the third conductor through the third switch without requiring selectable connection through another conductor;

selectively coupling the second conductor to the fourth conductor through the fourth switch without requiring selectable connection through another conductor; and

selectively coupling the sixth conductor to the seventh conductor through the fifth switch without requiring selectable connection through another conductor.

23. The method as set forth in claim 18, further comprising:

providing a third switch in the first region;

selectively coupling the first conductor to drive the second conductor through at least the third switch;

providing a fourth switch in the first region; and

selectively coupling the third conductor to drive the fourth conductor through at least the fourth switch.

24. An integrated circuit, comprising:

a first region comprising;

a first plurality of cells located along a first dimension and a second dimension, wherein the first region has a first span along the first dimension and a second span along the second dimension;

a first conductor located within the first region having a first span along the first dimension;

a second conductor located within the first region having a second span along the second dimension; and

wherein the first conductor and the second conductor are neither inputs nor outputs of any cells;

a second region comprising;

first, second, third and fourth replicated first regions, wherein the first replicated first region and the second replicated first region are located adjacent in a first row along the first dimension, wherein the third replicated first region and the fourth replicated first region are located in a second row along the first dimension, wherein the first row of first replicated first region and second replicated first region and the second row of third replicated first region and fourth replicated first region are located adjacent in a column along the second dimension, wherein the second region has a third span along the first dimension and a fourth span along the second dimension;

a third conductor located within the second region having a third span along the first dimension;

a fourth conductor located within the second region having a fourth span along the second dimension, wherein the third conductor and the fourth conductor are neither inputs nor outputs of any cells;

a first switch, wherein the third conductor is selectively coupleable to the fourth conductor through the first switch without requiring selectable connection through another conductor; and

wherein the third span of the third conductor is greater than the first span of the first region along the first dimension, and wherein the fourth span of the fourth conductor is greater than the second span of the first region along the second dimension;

a third region comprising;

first, second, third and fourth replicated second regions, wherein the first replicated second region and the second replicated second region are located adjacent in a first row along the first dimension and the third replicated second region and the fourth replicated second region are located adjacent in a second row along the first dimension, wherein the first row of the first replicated second region and the second replicated second region and the second row of the third replicated second region and the fourth replicated second region are located in a column along the second dimension;

a fifth conductor located within the third region having a fifth span along the first dimension;

a sixth conductor located within the third region having a sixth span along the second dimension, wherein the fifth conductor and the sixth conductor are neither inputs nor outputs of any cells;

a second switch, wherein the fifth conductor is selectively coupleable to the sixth conductor through the second switch without requiring selectable connection through another conductor; and

wherein the fifth span of the fifth conductor is greater than the third span of the second region along the first dimension and wherein the sixth span of the sixth conductor is greater than the fourth span of the second region along the second dimension.

25. A method of constructing an integrated circuit, comprising:

providing a first region comprising a first plurality of cells;

disposing the cells of the first plurality of cells along a first dimension and a second dimension, wherein the first region has a first span along the first dimension and a second span along the second dimension;

disposing a first conductor within the first region having a first span along the first dimension;

disposing a second conductor within the first region having a second span along the second dimension, wherein the first conductor and the second conductor are neither inputs nor outputs of any cells;

providing a second region comprising first, second, third and fourth replicated first regions;

disposing the first replicated first region and the second replicated first region adjacent in a first row along the first dimension and disposing the third replicated first region and the fourth replicated first region adjacent in a second row along the first dimension;

disposing the first row of first replicated first region and second replicated first region and the second row of third replicated first region and fourth replicated first region adjacent in a column along the second dimension, wherein the second region has a third span along the first dimension and a fourth span along the second dimension;

disposing a third conductor within the second region having a third span along the first dimension;

disposing a fourth conductor within the second region having a fourth span along the second dimension, wherein the third conductor and the fourth conductor are neither inputs nor outputs of any cells;

providing a first switch to selectively couple the third conductor to the fourth conductor through the first switch without requiring selectable connection through another conductor, wherein the third span of the third conductor is greater than the first span of the first region along the first dimension, and wherein the fourth span of the fourth conductor is greater than the second span of the first region along the second dimension;

providing a third region comprising first, second, third and fourth replicated second regions;

disposing the first replicated second region and the second replicated second region adjacent in a first row along the first dimension and disposing the third replicated second region and the fourth replicated second region adjacent in a second row along the first dimension;

disposing the first row of the first replicated second region and the second replicated second region and the second row of the third replicated second region and the fourth replicated second region in a column along the second dimension, wherein the third region has a fifth span along the first dimension and a sixth span along the second dimension;

disposing a fifth conductor within the third region having a fifth span along the first dimension;

disposing a sixth conductor within the third region having a sixth span along the second dimension, wherein the fifth conductor and the sixth conductor are neither inputs nor outputs of any cells; and

providing a second switch to selectively couple the fifth conductor to the sixth conductor through the second switch without requiring selectable connection through another conductor, wherein the fifth span of the fifth conductor is greater than the third span of the second region along the first dimension, and wherein the sixth span of the sixth conductor is greater than the fourth span of the second region along the second dimension.