Scheduling logic on a programmable device implemented using a high-level language
First Claim
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1. A method for implementing a programmable device, the method comprising:
- receiving high-level language code, the high-level language code configured to run on a conventional central processing unit;
generating hardware acceleration logic for performing the high-level language code on a programmable device, wherein the hardware acceleration logic is configured to perform pipelined execution of instructions using a plurality of execution stages, the hardware acceleration logic having access to an allocated region of memory, the hardware acceleration logic further having associated read and write ports for handling pointer referencing and dereferencing to addresses outside of the allocate region of memory;
coupling the hardware acceleration logic to memory to allow the hardware acceleration logic to access memory, wherein the number of stages included in the hardware acceleration logic is associated with the expected latency of memory access.
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Abstract
Methods and apparatus are provided for implementing a programmable device including a processor core, a hardware accelerator, and secondary components such as memory. A portion of a program written in a high-level language is automatically selected for hardware acceleration. Dedicated ports are generated to allow the hardware accelerator to handle pointer referencing and dereferencing. A hardware accelerator is generated to perform pipelined processing of instructions. The number of stages implemented for pipelined processing is at least partially dependent on the latency associated with accessing secondary components.
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Citations
30 Claims
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1. A method for implementing a programmable device, the method comprising:
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receiving high-level language code, the high-level language code configured to run on a conventional central processing unit; generating hardware acceleration logic for performing the high-level language code on a programmable device, wherein the hardware acceleration logic is configured to perform pipelined execution of instructions using a plurality of execution stages, the hardware acceleration logic having access to an allocated region of memory, the hardware acceleration logic further having associated read and write ports for handling pointer referencing and dereferencing to addresses outside of the allocate region of memory; coupling the hardware acceleration logic to memory to allow the hardware acceleration logic to access memory, wherein the number of stages included in the hardware acceleration logic is associated with the expected latency of memory access. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18)
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19. A programmable device, comprising:
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a hardware acceleration component on a programmable device operable to implement high-level language code configured to run on a conventional central processing unit;
wherein the hardware acceleration component is configured to perform pipelined execution of instructions using a plurality of execution stages, the hardware acceleration logic having access to an allocated region of memory, the hardware acceleration logic further having associated read and write ports for handling pointer referencing and dereferencing to addresses outside of the allocate region of memory;memory coupled to the hardware acceleration component, wherein the number of execution stages is associated with the expected latency of memory access. - View Dependent Claims (20, 21, 22, 23, 24, 25)
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26. A system for implementing a programmable device, the system comprising:
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means for receiving high-level language code, the high-level language code configured to run on a conventional central processing unit; means for generating hardware acceleration logic for performing the high-level language code on a programmable device, wherein the hardware acceleration logic is configured to perform pipelined execution of instructions using a plurality of execution stages, the hardware acceleration logic having access to an allocated region of memory, the hardware acceleration logic further having associated read and write ports for handling pointer referencing and dereferencing to addresses outside of the allocate region of memory; means for coupling the hardware acceleration logic to a secondary component to allow the hardware acceleration logic to access the secondary component, wherein the number of stages included in the hardware acceleration logic is associated with the expected latency of secondary component access. - View Dependent Claims (27, 28, 29, 30)
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Specification