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Scheduling logic on a programmable device implemented using a high-level language

  • US 7,409,670 B1
  • Filed: 11/16/2004
  • Issued: 08/05/2008
  • Est. Priority Date: 04/01/2004
  • Status: Active Grant
First Claim
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1. A method for implementing a programmable device, the method comprising:

  • receiving high-level language code, the high-level language code configured to run on a conventional central processing unit;

    generating hardware acceleration logic for performing the high-level language code on a programmable device, wherein the hardware acceleration logic is configured to perform pipelined execution of instructions using a plurality of execution stages, the hardware acceleration logic having access to an allocated region of memory, the hardware acceleration logic further having associated read and write ports for handling pointer referencing and dereferencing to addresses outside of the allocate region of memory;

    coupling the hardware acceleration logic to memory to allow the hardware acceleration logic to access memory, wherein the number of stages included in the hardware acceleration logic is associated with the expected latency of memory access.

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