Techniques for sensing temperature and automatic calibration on integrated circuits

• US 7,410,293 B1
• Filed: 05/17/2006
• Issued: 08/12/2008
• Est. Priority Date: 03/27/2006
• Status: Active Grant

• Current Assignee: Tahoe Research Limited (f/k/a Learndale Limited) (Vector Capital Corporation)
• Original Assignee: Altera Corporation (Intel Corporation)
• Inventors: Santurkar, Vikram, Doan, Quyen
• Primary Examiner(s): Verbitsky; Gail
• Assistant Examiner(s): Jagan; Mirellys
• Application Number:
  US11/383,937
• Time in Patent Office: 818 Days
• Field of Search: 374/178, 374/170, 374/171, 374/172
• US Class Current: 374/178
• CPC Class Codes: G01K 15/00 Testing or calibrating of thermometers
• CPC Class Codes: G01K 2219/00 Thermometers with dedicated analog to digital converters
• CPC Class Codes: G01K 7/015 using microstructures, e.g. made of silicon

Abstract

Techniques are provided for sensing the temperature of an integrated circuit (IC). A diode is provided on an IC. The voltage across the diode varies with the temperature of the IC. A feedback loop is coupled around the diode to monitor the voltage across the diode. The feedback loop contains a comparator and logic circuitry that outputs a digital code. The digital code varies in response to changes in the diode voltage. The value of the digital code can be used to determine the temperature on the IC. Techniques are also provided for automatically calibrating a temperature sensing circuit to compensate for inaccuracies caused by variations in process, temperature, and supply voltage. A calibration circuit is added to the feedback loop in the temperature sensor. The calibration circuit generates an offset code that is used to adjust the digital code to compensate for variations in temperature, process, and supply voltage.

Claims

1. An integrated circuit comprising a temperature sensing circuit, wherein the temperature sensing circuit comprises:

a diode;

a comparator coupled to receive a signal from the diode;

a logic circuit coupled to receive an output of the comparator, the logic circuit generating a plurality of digital output signals; and

a first transistor network comprising a first plurality of transistors that are coupled in parallel to receive the plurality of digital output signals from the logic circuit, and a first plurality of resistors, wherein each of the first plurality of resistors is coupled in series with one of the first plurality of transistors.

2. The integrated circuit defined in claim 1 further comprising:

an offset resistor coupled to the plurality of resistors.

3. The integrated circuit defined in claim 1 further comprising:

a pin coupled to the diode and an input of the comparator.

4. The integrated circuit defined in claim 1 wherein the plurality of transistors are binary weighted, and the plurality of resistors are binary weighted.

5. The integrated circuit defined in claim 1 further comprising:

a multiplexer coupled to an input of the comparator, wherein a first input of the multiplexer is coupled to the diode;

a first switch coupled to a second input of the multiplexer and a pin; and

a second switch coupled to the pin and the diode.

6. The integrated circuit defined in claim 1 wherein the integrated circuit is a field programmable gate array.

7. The integrated circuit defined in claim 1 further comprising:

a voltage reference circuit generating a reference voltage; and

a multiplexer having a first input coupled to receive the reference voltage, a second input coupled to receive a signal from the diode, and an output coupled to the comparator.

8. The integrated circuit defined in claim 7 further comprising:

an offset calibration circuit coupled to receive the output of the comparator; and

a second transistor network coupled to receive an offset code from the offset calibration circuit and coupled to the first transistor network, the second transistor network comprising a second plurality of transistors and a second plurality of resistors, each coupled in series with one of the second plurality of transistors.

9. The integrated circuit defined in claim 8 further comprising:

an adder circuit coupled to add the offset code from the offset calibration circuit to a fixed calibration code and to transmit an output code to the second transistor network.

10. A method for sending temperature on an integrated circuit, the method comprising:

comparing a voltage across a diode with a voltage from a first transistor network using a comparator, the first transistor network comprising first transistors coupled in parallel and first resistors coupled in series with the first transistors;

converting an output of the comparator into a plurality of digital signals; and

selectively enabling the first transistors in the first transistor network in response to the plurality of digital signals.

11. The method defined in claim 10 further comprising:

coupling the diode to a pin of the integrated circuit.

12. The method defined in claim 10 further comprising:

coupling an offset resistor between the first resistors and a supply voltage.

13. The method defined in claim 10 wherein the first transistors are binary weighted and the first resistors are binary weighted.

14. The method defined in claim 10 wherein the comparator and the first transistor network comprise a dual purpose temperature sensing circuit and an on-chip calibration circuit.

15. The method defined in claim 10 further comprising:

generating a reference voltage that is independent of process, voltage, and temperature variations;

coupling the reference voltage to an input of the comparator using a multiplexer;

maintaining states of the first transistors constant while the reference voltage is coupled to the comparator;

generating a digital offset code in response to the output of the comparator; and

selectively enabling second transistors in a second transistor network in response to the digital offset code, wherein the second transistor network includes second resistors coupled in series with the second transistors, and the second transistor network is coupled to the first transistor network.

16. The method defined in claim 15 further comprising:

coupling the diode to the input of the comparator using the multiplexer; and

maintaining the digital offset code constant while the diode is coupled to the comparator.

17. The method defined in claim 15 further comprising:

adding the digital offset code to a fixed offset code to generate an adjusted offset code that is used to selectively enable the second transistors.

18. An integrated circuit comprising:

a comparator;

an offset calibration circuit that generates a digital offset code in response to the output signal of the comparator;

a first transistor network selectively enabling first transistors in response to the digital offset code;

a logic circuit that generates second digital output signals in response to an output signal of the comparator; and

a second transistor network selectively enabling second transistors in response to the second digital signals,

wherein the comparator is coupled to receive a signal from the first and the second transistor networks, and states of second transistors in the second transistor network are held constant in response to a predefined digital code during an offset calibration mode.

19. The integrated circuit defined in claim 18 wherein the digital offset code remains constant during a temperature sensing mode, while the logic circuit controls states of the second transistors in the second transistor network.

20. The integrated circuit defined in claim 19 further comprising:

a multiplexer coupled to an input of the comparator;

a voltage reference circuit coupled to a first input of the multiplexer; and

a diode coupled to a second input of the multiplexer.