Post last wiring level inductor using patterned plate process

• US 7,410,894 B2
• Filed: 07/27/2005
• Issued: 08/12/2008
• Est. Priority Date: 07/27/2005
• Status: Expired due to Fees

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: He, Zhong-Xiang, Chinthakindi, Anil K., Gambino, Jeffrey P., Coolbaugh, Douglas D., Stamper, Anthony K., Vaed, Kunal, Florkey, John E.
• Primary Examiner(s): TRINH, MICHAEL MANH
• Application Number:
  US11/161,217
• Publication Number:
  US 20070026659A1
• Time in Patent Office: 1,112 Days
• Field of Search: 438/612, 438/381, 438/622, 257/531
• US Class Current: 438/612
• CPC Class Codes: H01L 21/76804 by forming tapered via holes
• CPC Class Codes: H01L 21/76807 for dual damascene structures
• CPC Class Codes: H01L 21/76808 involving intermediate temporary filling with material
• CPC Class Codes: H01L 21/76814 post-treatment or after-treatment, e.g. cleaning or removal of oxides on underlying conductors
• CPC Class Codes: H01L 21/76834 formation of thin insulating films on the sidewalls or on top of conductors H01L21/76831 takes precedence
• CPC Class Codes: H01L 21/76852 the layer also covering the sidewalls of the conductive structure
• CPC Class Codes: H01L 21/76865 Selective removal of parts of the layer H01L21/76844 takes precedence
• CPC Class Codes: H01L 21/76879 by selective deposition of conductive material in the vias, e.g. selective C.V.D. on semiconductor material, plating plating on semiconductors in general H01L21/288
• CPC Class Codes: H01L 21/76885 By forming conductive members before deposition of protective insulating material, e.g. pillars, studs
• CPC Class Codes: H01L 2221/1036 Dual damascene with different via-level and trench-level dielectrics
• CPC Class Codes: H01L 23/5227 Inductive arrangements or effects of, or between, wiring layers other inductive arrangements H01L23/645
• CPC Class Codes: H01L 23/53238 Additional layers associated with copper layers, e.g. adhesion, barrier, cladding layers
• CPC Class Codes: H01L 28/10 Inductors
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A method of forming a semiconductor structure, and the semiconductor structure so formed, wherein a transmission line, such as an inductor, is formed on a planar level above the surface of a last metal wiring level.

Claims

1. A method of forming a semiconductor substrate, comprising:

providing a substrate having at least one metal wiring level within the substrate;

depositing a first insulative layer on a surface of the substrate;

forming a wire bond pad within the first insulative layer;

depositing a second insulative layer on the first insulative layer and the wire bond pad; and

forming an inductor within the second insulative layer using a patterned plate process, wherein the inductor is formed substantially co-planar with at least a portion of the wire bond pad, wherein forming the inductor further comprises;

depositing a liner on the surface of the substrate and on a surface within an at least one opening within the second insulative layer;

depositing a seed layer on a surface of the liner;

removing a portion of the seed layer from the surface of the substrate, leaving the seed layer within the at least one opening within the second insulative layer;

depositing a conductive material within the at least one opening within the second insulative layer, such that the conductive material extends above the surface of the substrate; and

planarizing the surface of the substrate to remove excess conductive material extending above the surface of the substrate.

2. The method of claim 1, following planarizing the surface of the substrate, further comprising:

removing at least a portion of the second insulative layer;

depositing a dielectric layer on the surface of the substrate; and

forming an opening within the dielectric layer down to the wire bond pad.

3. The method of claim 1, further comprising:

before said forming the wire bond pad, depositing a first dielectric layer over the surface of the substrate such that the first dielectric layer is disposed between the substrate and the first insulative layer and is in direct mechanical contact with the substrate and the first insulative layer; and

forming an opening within the first dielectric layer and the first insulative layer down to the at least one metal wiring level within the substrate.

4. The method of claim 3, wherein said forming the wire bond pad comprises forming the wire bond pad in and above the opening such that portions of an exterior surface of the wire bond pad are disposed in the second insulative layer.

5. The method of claim 4, wherein the dielectric layer prevents copper within a wire in the at least one metal wiring level from diffusing into the first insulative layer.

6. The method of claim 4, wherein the method further comprises:

after said forming the inductor, removing the second insulative layer such that the inductor remains after said removing the second insulative layer has been performed;

after said removing the second insulative layer, forming a second dielectric layer on and in direct mechanical contact with the first insulative layer such that the second dielectric layer completely covers and is in direct mechanical contact with both the inductor and the exterior surface of the wire bond pad, wherein said portions of the exterior surface of the wire bond pad are disposed in the second dielectric layer.

7. The method of claim 6, wherein the method further comprises removing a first portion of the second dielectric layer to uncover a fractional portion of the exterior surface of the wire bond pad such that both the inductor and a remaining portion of the exterior surface of the wire bond pad remain completely covered by a remaining portion of the second dielectric layer.

8. The method of claim 7,

wherein a first portion of the exterior surface of the wire bond pad is disposed between a second portion of the exterior surface of the wire bond pad and a third portion of the exterior surface of the wire bond pad;

wherein the fractional portion of the exterior surface of the wire bond pad comprises the first portion of the exterior surface of the wire bond pad, a first part of the second portion of the exterior surface of the wire bond pad, and a first part of the third portion of the exterior surface of the wire bond pad;

wherein the remaining portion of the exterior surface of the wire bond pad comprises a second part of the second portion of the exterior surface of the wire bond pad and a second part of the third portion of the exterior surface of the wire bond pad.