Ion trap in a semiconductor chip
First Claim
1. An ion trap device, comprising:
- a semiconductor chip, including;
a first substrate portion;
a first insulator layer disposed on the first substrate portion;
a first electrode layer disposed on the first insulator layer, wherein a first electrode system is formed on a surface thereof;
a second substrate portion spaced and opposed to the first substrate portion so as to define a first aperture formed therebetween;
a second insulator layer disposed on the second substrate portion spaced and opposed to the first insulator layer so as to define a second aperture formed therebetween;
a second electrode layer disposed on the second insulator layer, wherein a second electrode system is formed on a surface thereof, wherein the second electrode layer is spaced and opposed to the first electrode layer so as to define a third aperture formed therebetween;
a third insulator layer disposed on the first electrode layer;
a third electrode layer disposed on the third insulator layer, wherein a third electrode system is formed on a surface thereof;
a fourth insulator layer disposed on the second electrode layer spaced and opposed to the third insulator layer so as to define a fourth aperture formed therebetween; and
a fourth electrode layer disposed on the fourth insulator layer, wherein a fourth electrode system is formed on a surface thereof, wherein the fourth electrode layer is spaced and opposed to the third electrode layer so as to define a fifth aperture formed therebetween;
wherein the first, second, third, fourth, and fifth apertures are substantially axially aligned so as to define the at least one ion trapping region selectively operable to receive at least one ion introduced therein;
wherein the first, second, third and fourth electrode systems are selectively operable to form the ion trap in the ion trapping region when a voltage is selectively applied to the first, second, third and fourth electrode systems.
3 Assignments
0 Petitions
Accused Products
Abstract
A micrometer-scale ion trap, fabricated on a monolithic chip using semiconductor micro-electromechanical systems (MEMS) technology. A single 111Cd+ ion is confined, laser cooled, and the heating measured in an integrated radiofrequency trap etched from a doped gallium arsenide (GaAs) heterostructure. Single 111Cd+ qubit ions are confined in a radiofrequency linear ion trap on a semiconductor chip by applying a combination of static and oscillating electric potentials to integrated electrodes. The electrodes are lithographically patterned from a monolithic semiconductor substrate, eliminating the need for manual assembly and alignment of individual electrodes. The scaling of this structure to hundreds or thousands of electrodes is possible with existing semiconductor fabrication technology.
62 Citations
67 Claims
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1. An ion trap device, comprising:
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a semiconductor chip, including; a first substrate portion; a first insulator layer disposed on the first substrate portion; a first electrode layer disposed on the first insulator layer, wherein a first electrode system is formed on a surface thereof; a second substrate portion spaced and opposed to the first substrate portion so as to define a first aperture formed therebetween; a second insulator layer disposed on the second substrate portion spaced and opposed to the first insulator layer so as to define a second aperture formed therebetween; a second electrode layer disposed on the second insulator layer, wherein a second electrode system is formed on a surface thereof, wherein the second electrode layer is spaced and opposed to the first electrode layer so as to define a third aperture formed therebetween; a third insulator layer disposed on the first electrode layer; a third electrode layer disposed on the third insulator layer, wherein a third electrode system is formed on a surface thereof; a fourth insulator layer disposed on the second electrode layer spaced and opposed to the third insulator layer so as to define a fourth aperture formed therebetween; and a fourth electrode layer disposed on the fourth insulator layer, wherein a fourth electrode system is formed on a surface thereof, wherein the fourth electrode layer is spaced and opposed to the third electrode layer so as to define a fifth aperture formed therebetween; wherein the first, second, third, fourth, and fifth apertures are substantially axially aligned so as to define the at least one ion trapping region selectively operable to receive at least one ion introduced therein; wherein the first, second, third and fourth electrode systems are selectively operable to form the ion trap in the ion trapping region when a voltage is selectively applied to the first, second, third and fourth electrode systems. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18)
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19. A method of making an ion trap device, comprising:
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providing a substrate layer comprised of a conductive material; disposing a first insulator layer on the substrate layer; disposing a first membrane layer comprised of a conductive material on the first insulator layer; disposing a second insulator layer on the first membrane layer; disposing a second membrane layer on the second insulator layer; back etching a bottom surface of the substrate layer to form a wedge portion defining a first substrate portion and a second spaced and opposed substrate portion, wherein a portion of a lower surface of the first insulator layer is exposed; plasma etching a top surface of the second membrane layer to expose a portion of the first membrane layer; plasma etching a portion of the first and second membrane layers and first and second insulator layers to expose a top surface of the substrate layer; disposing an electrical contact member on spaced and opposed locations of the first and second membrane layers and the substrate layer; plasma etching through an axis of the first and second membrane layers and the first and second insulator layers to define first, second, third and fourth membrane portions and first, second, third and fourth insulator portions, wherein an area defining a second aperture is formed between spaced and opposed first and second insulator portions, wherein an area defining a third aperture is formed between spaced and opposed first and second membrane portions;
wherein an area defining a fourth aperture is formed between spaced and opposed third and fourth insulator portions, and wherein an area defining a fifth aperture is formed between spaced and opposed third and fourth membrane portions; andacid etching end portions of the first, second, third and fourth insulator portions such that the first, second, third and fourth membrane layers, respectively, are in a cantilever arrangement therewith. - View Dependent Claims (20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37)
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38. A semiconductor-chip-based ion trap device for trapping at least one ion, comprising:
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a first electrode assembly having at least three segmented cantilevered electrodes, with each cantilevered electrode segment having stacked upper and lower electrode members spaced apart by an insulating layer, with each electrode member having a proximate end with a contact pad and a distal end; and a second electrode assembly identical or substantially identical to the first electrode assembly and arranged in opposition thereto with the electrode distal ends in proximity to one another to form a gap that defines a free-space ion-trap region wherein the at least one ion is trapped when an electrical potential is applied to the first and second electrode assemblies. - View Dependent Claims (39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51, 52, 53)
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54. A method of trapping at least one ion, comprising:
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providing opposing first and second electrode assemblies, with each assembly having at least three segmented cantilevered electrodes, with each cantilevered electrode segment having stacked upper and lower electrode members spaced apart by an insulating layer, with each electrode member having a proximate end with a contact pad and a distal end, with the first and second assemblies arranged in opposition with the electrode distal ends in proximity to one another to form a gap that defines a free-space ion-trap region wherein the at least one ion is trapped when an electrical potential is applied to the first and second electrode assemblies; introducing the at least one ion into the ion-trap region; and applying said electrical potential so as to trap the at least one ion in the ion-trap region. - View Dependent Claims (55, 56, 57, 58, 59, 63, 66, 67)
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60. A method of fabricating an ion trap device for trapping at least one ion, comprising:
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forming a first electrode assembly having at least three segmented cantilevered electrodes, including providing each cantilevered electrode segment with stacked upper and lower electrode members spaced apart by an insulating layer, with each electrode member having a proximate end with a contact pad and a distal end; and forming a second electrode assembly identical or substantially identical to the first electrode assembly so as to be arranged in opposition thereto with the electrode distal ends in proximity to one another to form a gap that defines a free-space ion-trap region wherein the at least one ion is trapped when an electrical potential is applied to the first and second electrode assemblies. - View Dependent Claims (61, 62, 64, 65)
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Specification