Arithmetic processing apparatus
First Claim
1. An arithmetic processing apparatus that can be reconfigured in accordance with a processing mode, comprising a plurality of arranged unit arithmetic circuits,wherein each of said unit arithmetic circuits includes:
- at least one input terminal;
at least one output terminal;
a first register that holds data;
an adder operable to add two items of data;
a second resister that holds data;
a bit shifter operable to shift data to one of a left and a right direction;
a subtractor operable to calculate a difference between two items of data;
an absolute value calculating unit operable to calculate an absolute value of data; and
a path setting unit operable to set a connection path according to the processing mode, the connection path connecting among said input terminal, said output terminal, said first register, said adder, said second register, said bit shifter, said subtractor, and said absolute value calculating unit,wherein combinations of unit arithmetic circuits form a plurality of arithmetic processing blocks, and each of the plurality of arithmetic processing blocks has a unique arithmetic processing function that differs depending on the processing mode, andwherein the plurality of arithmetic processing blocks include first and second arithmetic processing blocks when the processing mode is a coding mode for a still picture,the first arithmetic processing block has a partial function for a discrete cosine transform processing using a distributed arithmetic method, andthe second arithmetic processing block has a digital filtering function.
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Accused Products
Abstract
The arithmetic processing apparatus of the present invention is an arithmetic processing apparatus that can be reconfigured in accordance with a processing mode and has a plurality of arranged unit arithmetic circuits. Each unit arithmetic circuit includes at least one input terminal, at least one output terminal, a first register which holds data, an adder which calculates a sum of two pieces of data, a second register which holds data, a bit shifter which shifts data left or right, a subtractor which calculates a difference between two pieces of data, an absolute value calculating unit which calculates an absolute value of data, and a path setting unit which sets a path according to the processing mode connecting among these circuit elements.
246 Citations
22 Claims
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1. An arithmetic processing apparatus that can be reconfigured in accordance with a processing mode, comprising a plurality of arranged unit arithmetic circuits,
wherein each of said unit arithmetic circuits includes: -
at least one input terminal; at least one output terminal; a first register that holds data; an adder operable to add two items of data; a second resister that holds data; a bit shifter operable to shift data to one of a left and a right direction; a subtractor operable to calculate a difference between two items of data; an absolute value calculating unit operable to calculate an absolute value of data; and a path setting unit operable to set a connection path according to the processing mode, the connection path connecting among said input terminal, said output terminal, said first register, said adder, said second register, said bit shifter, said subtractor, and said absolute value calculating unit, wherein combinations of unit arithmetic circuits form a plurality of arithmetic processing blocks, and each of the plurality of arithmetic processing blocks has a unique arithmetic processing function that differs depending on the processing mode, and wherein the plurality of arithmetic processing blocks include first and second arithmetic processing blocks when the processing mode is a coding mode for a still picture, the first arithmetic processing block has a partial function for a discrete cosine transform processing using a distributed arithmetic method, and the second arithmetic processing block has a digital filtering function.
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2. An arithmetic processing apparatus that can be reconfigured in accordance with a processing mode, comprising a plurality of arranged unit arithmetic circuits,
wherein each of said unit arithmetic circuits includes: -
at least one input terminal; at least one output terminal; a first register that holds data; an adder operable to add two items of data; a second register that holds data; a bit shifter operable to shift data to one of a left and a right direction; a subtractor operable to calculate a difference between two items of data; an absolute value calculating unit operable to calculate an absolute value of data; and a path setting unit operable to set a connection path according to the processing mode, the connection path connecting among said input terminal, said output terminal, said first register, said adder, said second register, said bit shifter, said subtractor, and said absolute value calculating unit, wherein combinations of unit arithmetic circuits form a plurality of arithmetic processing blocks, and each of the plurality of arithmetic processing blocks has a unique arithmetic processing function that differs depending on the processing mode, and wherein the plurality of arithmetic processing blocks include first, second and third arithmetic processing blocks when the processing mode is a coding mode for a moving picture using a correlation between moving picture frames, the first arithmetic processing block has a motion estimation function for a motion compensation interframe prediction coding, the second arithmetic processing block has a partial function for a discrete cosine transform processing using a distributed arithmetic method, and the third arithmetic processing block has a digital filtering function.
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3. An arithmetic processing apparatus that can be reconfigured in accordance with a processing mode, comprising a plurality of arranged unit arithmetic circuits,
wherein each of said unit arithmetic circuits includes: -
at least one input terminal; at least one output terminal; a first register that holds data; an adder operable to add two items of data; a second register that holds data; a bit shifter operable to shift data to one of a left and a right direction; a subtractor operable to calculate a difference between two items of data; an absolute value calculating unit operable to calculate an absolute value of data; and a path setting unit operable to set a connection path according to the processing mode, the connection path connecting among said input terminal, said output terminal, said first register, said adder, said second register, said bit shifter, said subtractor, and said absolute value calculating unit, wherein combinations of unit arithmetic circuits form a plurality of arithmetic processing blocks, and each of the plurality of arithmetic processing blocks has a unique arithmetic processing, function that differs depending on the processing mode, and wherein said at least one input terminal, includes first, second, and third input terminals, said at least one output terminal includes first and second output terminals, and said path setting unit includes; a first selector operable to select, according to the processing mode, one of picture data inputted from the second input terminal and picture data inputted from the third input terminal; a second selector operable to select, according to the processing mode, one of picture data outputted from said first register, picture data outputted from said second register, picture data inputted from the third input terminal and fixed data; and a third selector which i) selects, according to the processing mode, one of the picture data outputted from said second register, difference data outputted from said subtractor, and absolute value data outputted from said absolute value calculating unit and ii) outputs the selected data to a first input port of said adder, said first register holds the picture data inputted from the first input terminal in synchronization with a clock signal, said adder includes a first input port and a second input port i) adds the picture data outputted from said first register and inputted to the second input port to the picture data inputted to the first input port and ii) outputs the added data to the first output terminal, said second register holds the picture data outputted from said first selector in synchronization with the clock signal, said bit shifter shifts the picture data outputted from said second register as many as a set number of bits to one of an upper side and a lower side, said subtractor i) calculates a difference between the picture data outputted from said bit shifter and one of the picture data outputted from said second selector and the fixed data and ii) outputs the difference data to the second output terminal, and said absolute value calculating unit calculates an absolute value of the difference data.
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4. An arithmetic processing apparatus that can be reconfigured in accordance with a processing mode, comprising an arranged plurality of unit arithmetic circuits,
wherein each of the plurality of unit arithmetic circuits includes: -
first and second input terminals; third and fourth input terminals; a first register operable to hold picture data inputted from the first input terminal in synchronization with a clock signal; a first selector operable to select and output, according to the processing mode, one of picture data inputted from the second input terminal and picture data inputted from the third input terminal; an adder having a first input port and a second input port operable to i) add picture data outputted from the first register and inputted to the first input port and picture data inputted to the second input port and ii) output to a first output terminal; a second register operable to hold the picture data outputted from the first selector in synchronization with the clock signal; a second selector operable to select and output, according to the processing mode, one of the picture data outputted from the first register, the picture data outputted from the second register, the picture data inputted from the third input terminal, and fixed data; a bit shifter operable to shift the picture data outputted from the second register as many as a number of set bits to one of an upper side and a lower side; a subtractor operable to i) calculate a difference between the picture data outputted from the bit shifter and one of the picture data outputted from the second selector and the fixed data and ii) output the difference to a second output terminal; an absolute value calculating unit operable to calculate an absolute value of the difference data outputted from the subtractor; and a third selector operable to i) select, according to the processing mode, one of the picture data outputted from the second register, the difference data outputted from the subtractor, and the absolute value data outputted from the absolute value calculating unit and ii) output the selected data to the second input port of the adder, wherein combinations of unit arithmetic circuits form a plurality of arithmetic processing blocks, and each of the plurality of arithmetic processing blocks has an arithmetic processing function and the arithmetic processing function differs depending on the processing mode, each arithmetic processing function of each of the plurality of arithmetic processing blocks being different from each other. - View Dependent Claims (5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20)
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21. A semiconductor device that can be reconfigured in accordance with a processing mode, comprising a plurality of arranged unit arithmetic circuits,
wherein each of the plurality of unit arithmetic circuits include: -
at least one input terminal; at least one output terminal; a first register that holds data; an adder operable to add two items of data; a second register that holds data; a bit shifter operable to shift data to one of a left and a right direction; a subtractor operable to calculate a difference between two items of data; an absolute value calculating unit operable to calculate an absolute value of data; and a path setting unit operable to set a path according to the processing mode, the path connecting among the input terminal, the output terminal, the first register, the adder, the second register, the bit shifter, the subtractor, and the absolute value calculating unit, wherein combinations of unit arithmetic circuits form a plurality, of arithmetic processing blocks, and each of the plurality of arithmetic processing blocks has a unique arithmetic processing function that differs depending on the processing mode, and wherein the plurality of arithmetic processing, blocks includes first and second arithmetic processing blocks when the processing mode is a coding mode for a still picture, the first arithmetic processing block has a partial function for a discrete cosine transform processing using a distributed arithmetic method, and the second arithmetic processing block has a digital filtering function.
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22. A semiconductor device that can be reconfigured in accordance with a processing mode, comprising a plurality of semiconductors,
wherein each of said semiconductors comprises: -
at least one input terminal; at least one output terminal; a first register that holds data; an adder operable to add two items of data; a second register that holds data; a bit shifter operable to shift data to one of a left and a right direction; a subtractor operable to calculate a difference between two items of data; an absolute value calculating unit operable to calculate an absolute value of data; and a path setting unit operable to set a connection path according to the processing mode, the connection path connecting among said input terminal, said output terminal, said first register, said adder, said second register, said bit shifter, said subtractor, and said absolute value calculating unit, wherein combinations of said semiconductors form a plurality of arithmetic processing blocks, and each of the plurality of arithmetic processing blocks has a unique arithmetic processing function that differs depending on the processing mode, and wherein the plurality of arithmetic processing blocks includes first, second and third arithmetic processing blocks when the processing mode is a coding mode for a moving picture using a correlation between moving picture frames, the first arithmetic processing block has a motion estimation function for a motion compensation interframe prediction coding, the second arithmetic processing block has a partial function for a discrete cosine transform processing using a distributed arithmetic method, and the third arithmetic processing block has a digital filtering function.
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Specification