Memory hub and access method having internal prefetch buffers

• US 7,412,566 B2
• Filed: 08/24/2006
• Issued: 08/12/2008
• Est. Priority Date: 06/20/2003
• Status: Expired due to Fees

• Current Assignee: Round Rock Research LLC
• Original Assignee: Micron Technology, Inc.
• Inventors: Jeddeloh, Joseph M., Lee, Terry R.
• Primary Examiner(s): BATAILLE, PIERRE MICHE
• Application Number:
  US11/510,150
• Publication Number:
  US 20060288172A1
• Time in Patent Office: 719 Days
• Field of Search: 711/137, 711/118, 711/154, 711/213, 711/145, 711/113, 711/112, 711/114, 710/22, 710/3, 710/100, 709/229, 709/250, 709/233, 709/104
• US Class Current: 711/137
• CPC Class Codes: G06F 12/0862 with prefetch
• CPC Class Codes: G06F 2212/6022 Using a prefetch buffer or dedicated prefetch cache
• CPC Class Codes: G06F 2212/6024 History based prefetching
• CPC Class Codes: G06F 2212/6026 Prefetching based on access pattern detection, e.g. stride based prefetch

Abstract

A memory module includes a memory hub coupled to several memory devices. The memory hub includes history logic that predicts on the basis of read memory requests which addresses in the memory devices from which date are likely to be subsequently read. The history logic applies prefetch suggestions corresponding to the predicted addresses to a memory sequencer, which uses the prefetch suggestions to generate prefetch requests that are coupled to the memory devices. Data read from the memory devices responsive to the prefetch suggestions are stored in a prefetch buffer. Tag logic stores prefetch addresses corresponding to addresses from which data have been prefetched. The tag logic compares the memory request addresses to the prefetch addresses to determine if the requested read data are stored in the prefetch buffer. If so, the requested data are read from the prefetch buffer. Otherwise, the requested data are read from the memory devices.

Claims

1. A system for prefetching data in a memory system comprising:

a link interface receiving memory requests for access to memory cells in at least one of a plurality of memory devices;

a memory device interface coupled to the memory devices, the memory device interface being operable to transfer memory requests to the memory devices for access to memory cells in at least one of the memory devices and to receive read data responsive to at least some of the memory requests; and

a prefetch circuit coupled to the link interface to receive memory requests from the link interface and coupled to the memory device interface to receive data from the memory cells, the prefetch circuit operable to predict addresses that are likely to be accessed in the memory devices based on the memory requests and to prefetch and store data from memory cells according to the predicted addresses, the prefetch circuit further operable to provide the prefetched data to the link interface responsive to subsequent memory requests, the prefetch circuit being configured to detect a pattern from which addresses to memory requests likely to be accessed are predicted, and to generate prefetch suggestions indicative of addresses corresponding to the predicted memory requests.

2. The system of claim 1 wherein the prefetch circuit is operable to group the predicted memory request addresses into a plurality of sets corresponding to respective strides, and causes the prefetched data received from the memory cells to be stored into a plurality of sections each corresponding to a respective stride.

3. The system of claim 1 wherein the prefetch circuit is operable to selectively enable prefetching data based on the nature of the memory requests received from the link interface.

4. The system of claim 3 wherein the prefetch circuit is operable to selectively enable prefetching based on a percentage of memory requests for read data from the stored prefetch data compared to read data from the memory cells.

5. The system of claim 1 wherein the prefetch circuit comprises a plurality of prefetch buffers coupled to the memory device interface for receiving and storing prefetched data from memory cells being accessed based on the predicted addresses.

6. The system of claim 5 wherein the plurality of prefetch buffers comprises a single static random access memory device partitioned into a plurality of sections corresponding a plurality of strides.

7. The system of claim 5 wherein the prefetch circuit comprises a data read control circuit coupled to the memory device interface, the link interface, and the plurality of prefetch buffers, the data read control circuit operable to determine from the memory requests received from the link interface if the data corresponding to the memory requests are stored in the plurality of prefetch buffers, the data read control circuit further operable to transfer data from the plurality of prefetch buffers if the requested data are stored in the plurality of prefetch buffers and to transfer data from the memory device interface if the data are stored in the memory cells.

8. The system of claim 7 wherein the data read control circuit comprises a tag logic unit coupled to the link interface and the plurality of prefetched buffers, the tag logic unit operable to store addresses of the prefetched data stored in the plurality of prefetch buffers, the tag logic unit further operable to receive memory requests from the link interface, compare the addresses of the received memory requests to the addresses of the stored prefetched data, and generate a hit control signal indicative of whether an address match was determined.

9. The system of claim 7 wherein the data read control circuit comprises a multiplexer having data inputs coupled to the plurality of prefetch buffers, to the tag logic unit and to the memory device interface, and a data output coupled to the link interface, the multiplexer operable to transfer the data input from the plurality of prefetch buffers to the data output responsive to an active hit control signal received from the tag logic unit, and to transfer the data input form the memory device interface to the data output responsive to an inactive hit control signal received from the tag logic unit.

10. The system of claim 1 wherein the prefetch circuit is further operable to prefetch data from memory cells that are currently accessed such that the prefetching does not require the selected memory cells to be precharged.

11. The system of claim 1 wherein the link interface comprises an optical input/output port.

12. A system for prefetching data in a memory system comprising:

a link interface receiving memory requests for access to memory cells in at least one of a plurality of memory devices;

a memory device interface coupled to the memory devices, the memory device interface being operable to transfer memory requests to the memory devices for access to memory cells in at least one of the memory devices and to receive read data responsive to at least some of the memory requests; and

a prefetch circuit coupled to the link interface to receive memory requests from the link interface and coupled to the memory device interface to receive data from the memory cells, the prefetch circuit operable to predict addresses that are likely to be accessed in the memory devices based on the memory requests and to prefetch and store data from memory cells according to the predicted addresses, the prefetch circuit further operable to provide the prefetched data to the link interface responsive to subsequent memory requests, the prefetch circuit comprising a single static random access memory device partitioned into a plurality of sections corresponding a plurality of strides and being coupled to the memory device interface for receiving and storing prefetched data from memory cells being accessed based on the predicted addresses.

13. A system for prefetching data in a memory system comprising:

a link interface receiving memory requests for access to memory cells in at least one of a plurality of memory devices;

a memory device interface coupled to the memory devices, the memory device interface being operable to transfer memory requests to the memory devices for access to memory cells in at least one of the memory devices and to receive read data responsive to at least some of the memory requests; and

a prefetch circuit coupled to the link interface to receive memory requests from the link interface and coupled to the memory device interface to receive data from the memory cells, the prefetch circuit operable to predict addresses that are likely to be accessed in the memory devices based on the memory requests and to prefetch and store data from memory cells according to the predicted addresses, the prefetch circuit further operable to provide the prefetched data to the link interface responsive to subsequent memory requests, the prefetch circuit further comprising;

a plurality of prefetch buffers coupled to the memory device interface for receiving and storing prefetched data from memory cells being accessed based on the predicted addresses; and

a data read control circuit coupled to the memory device interface, the link interface, and the plurality of prefetch buffers, the data read control circuit operable to determine from the memory requests received from the link interface if the data corresponding to the memory requests are stored in the plurality of prefetch buffers, the data read control circuit further operable to transfer data from the plurality of prefetch buffers if the requested data are stored in the plurality of prefetch buffers and to transfer data from the memory device interface if the data are stored in the memory cells.

14. The system of claim 13 wherein the data read control circuit comprises a tag logic unit coupled to the link interface and the plurality of prefetched buffers, the tag logic unit operable to store addresses of the prefetched data stored in the plurality of prefetch buffers, the tag logic unit further operable to receive memory requests from the link interface, compare the addresses of the received memory requests to the addresses of the stored prefetched data, and generate a hit control signal indicative of whether an address match was determined.

15. The system of claim 13 wherein the data read control circuit comprises a multiplexer having data inputs coupled to the plurality of prefetch buffers, to the tag logic unit and to the memory device interface, and a data output coupled to the link interface, the multiplexer operable to transfer the data input from the plurality of prefetch buffers to the data output responsive to an active hit control signal received from the tag logic unit, and to transfer the data input form the memory device interface to the data output responsive to an inactive hit control signal received from the tag logic unit.

16. A memory hub comprising:

a link interface receiving memory requests for access to memory cells in at least one of a plurality of memory device;

a memory device interface coupled to the memory devices, the memory device interface being operable to transfer memory requests to the memory devices for access to memory cells in at least one of the memory devices and to receive data responsive to at least some of the memory requests;

a prefetch circuit coupled to the link interface to receive memory requests from the link interface and coupled to the memory device interface to receive data from the memory cells, the prefetch circuit operable to predict addresses that are likely to be accessed in the memory devices based on the memory requests and generate prefetch suggestions indicative of the predicted addresses to prefetch data from memory cells, the prefetch circuit further operable to store the data that are prefetched and transfer the prefetch data to the link interface; and

a memory sequencer coupled to the link interface, the memory device interface and the prefetch circuit, the memory sequencer operable to transfer memory requests received from the link interface to the prefetch circuit to determine if the data corresponding to the memory requests are stored in the prefetch circuit, the memory sequencer further being operable to transfer memory requests received from the link interface to the memory device interface to fetch the data corresponding to the memory requests if the data are not stored in the prefetch circuit, the memory sequencer further being operable to generate prefetch requests responsive to the prefetch suggestions received from the prefetch circuit to fetch data corresponding to the prefetch suggestions.

17. The memory hub of claim 16 wherein the prefetch circuit is operable to detect a pattern from which addresses to memory requests likely to be accessed are predicted, and operable to generate prefetch suggestions indicative of addresses corresponding to the predicted memory requests.

18. The memory hub of claim 17 wherein the prefetch circuit is further operable to group the predicted memory request addresses into a plurality of sets corresponding to respective strides, and to cause the prefetched data received from the memory cells to be stored into a plurality of sections each corresponding to a respective stride.

19. The memory hub of claim 17 wherein the prefetch circuit is further operable to selectively enable prefetching data based on the nature of the memory requests received from the link interface.

20. The memory hub of claim 19 wherein the prefetch circuit is configured to selectively enable prefetching based on a percentage of memory requests for read data from the stored prefetch data compared to read data from the memory cells.

21. The memory hub of claim 16 wherein the prefetch circuit comprises a plurality of prefetch buffers coupled to the memory device interface for receiving and storing prefetched data from memory cells being accessed based on the prefetch suggestions.

22. The memory hub of claim 21 wherein the plurality of prefetch buffers comprises a single static random access memory device partitioned into a plurality of sections corresponding a plurality of strides.

23. The memory hub of claim 21 wherein the plurality of prefetch buffers comprises a plurality of registers that are enabled and partitioned according to a plurality of respective strides.

24. The memory hub of claim 21 wherein the prefetch circuit comprises a data read control circuit coupled to the memory device interface, the link interface, and the plurality of prefetch buffers, the data read control circuit operable to determine from the memory requests received from the link interface if the data corresponding to the memory requests are stored in the plurality of prefetch buffers, the data read control circuit further operable to transfer data from the plurality of prefetch buffers if the requested data are stored in the plurality of prefetch buffers and to transfer data from the memory device interface if the data are stored in the memory cells.

25. The memory hub of claim 24 wherein the data read control circuit comprises a tag logic unit coupled to the link interface and the plurality of prefetched buffers, the tag logic unit operable to store addresses of the prefetched data stored in the plurality of prefetch buffers, the tag logic unit further operable to receive memory requests from the link interface, compare the addresses of the received memory requests to the addresses of the stored prefetched data, and generate a hit control signal indicative of whether an address match was determined.

26. The memory of hub of claim 25 wherein the tag logic unit is further coupled the memory sequencer to which the hit control signal is applied, and wherein the memory sequencer is prevented from transferring a memory request to the memory device interface responsive to receiving an active hit control signal.

27. The memory hub of claim 24 wherein the data read control circuit comprises a multiplexer having data inputs coupled to the plurality of prefetch buffers, to the tag logic unit and to the memory device interface, and a data output coupled to the link interface, the multiplexer operable to transfer the data input from the plurality of prefetch buffers to the data output responsive to an active hit control signal received from the tag logic unit, and to transfer the data input from the memory device interface to the data output responsive to an inactive hit control signal received from the tag logic unit.

28. The memory hub of claim 16 wherein the memory sequencer is operable to generate and transfer prefetch requests to the memory device interface only when memory requests are not being transferred from the link interface to the memory sequencer.

29. The memory hub of claim 16 wherein the prefetch circuit is further operable to prefetch data from memory cells that are currently accessed such that the act of prefetching data does not require the selected memory cells to be precharged.

30. The memory hub of claim 16 wherein the link interface comprises an optical input/output port.

31. A computer system, comprising:

a central processing unit (“

CPU”

);

a system controller coupled to the CPU, the system controller having an input port and an output port;

an input device coupled to the CPU through the system controller;

an output device coupled to the CPU through the system controller;

a storage device coupled to the CPU through the system controller;

a plurality of memory modules, each of the memory modules comprising;

a plurality of memory devices; and

a system for prefetching data comprising;

a link interface receiving memory requests for access to memory cells in at least one of the memory devices;

a memory device interface coupled to the memory devices, the memory device interface being operable to transfer memory requests to the memory devices for access to memory cells in at least one of the memory devices and to receive read data responsive to at least some of the memory requests; and

a prefetch circuit coupled to the link interface to receive memory requests from the link interface and coupled to the memory device interface to receive data from the memory cells, the prefetch circuit operable to predict addresses that are likely to be accessed in the memory devices based on the memory requests and to prefetch and store data from memory cells according to the predicted addresses, the prefetch circuit further operable to provide the prefetched data to the link interface responsive to subsequent memory requests, the prefetch circuit being configured to detect a pattern from which addresses to memory requests likely to be accessed are predicted, and operable to generate prefetch suggestions indicative of addresses corresponding to the predicted memory requests.

32. The computer system of claim 31 wherein the prefetch circuit is operable to group the predicted memory request addresses into a plurality of sets corresponding to respective strides, and causes the prefetched data received from the memory cells to be stored into a plurality of sections each corresponding to a respective stride.

33. The computer system of claim 31 wherein the prefetch circuit is operable to selectively enable prefetching data based on the nature of the memory requests received from the link interface.

34. The computer system of claim 33 wherein the prefetch circuit is operable to selectively enable prefetching based on a percentage of memory requests for read data from the stored prefetch data compared to read data from the memory cells.

35. The computer system of claim 31 wherein the prefetch circuit comprises a plurality of prefetch buffers coupled to the memory device interface for receiving and storing prefetched data from memory cells being accessed based on the predicted addresses.

36. The computer system of claim 35 wherein the plurality of prefetch buffers comprises a single static random access memory device partitioned into a plurality of sections corresponding a plurality of strides.

37. The computer system of claim 35 wherein the prefetch circuit comprises a data read control circuit coupled to the memory device interface, the link interface, and the plurality of prefetch buffers, the data read control circuit operable to determine from the memory requests received from the link interface if the data corresponding to the memory requests are stored in the plurality of prefetch buffers, the data read control circuit further operable to transfer data from the plurality of prefetch buffers if the requested data are stored in the plurality of prefetch buffers and to transfer data from the memory device interface if the data are stored in the memory cells.

38. The computer system of claim 37 wherein the data read control circuit comprises a tag logic unit coupled to the link interface and the plurality of prefetched buffers, the tag logic unit operable to store addresses of the prefetched data stored in the plurality of prefetch buffers, the tag logic unit further operable to receive memory requests from the link interface, compare the addresses of the received memory requests to the addresses of the stored prefetched data, and generate a hit control signal indicative of whether an address match was determined.

39. The computer system of claim 37 wherein the data read control circuit comprises a multiplexer having data inputs coupled to the plurality of prefetch buffers, to the tag logic unit and to the memory device interface, and a data output coupled to the link interface, the multiplexer operable to transfer the data input from the plurality of prefetch buffers to the data output responsive to an active hit control signal received from the tag logic unit, and to transfer the data input form the memory device interface to the data output responsive to an inactive hit control signal received from the tag logic unit.

40. The computer system of claim 31 wherein the prefetch circuit is further operable to prefetch data from memory cells that are currently accessed such that the prefetching does not require the selected memory cells to be precharged.

41. The computer system of claim 31 wherein the link interface comprises an optical input/output port.

42. A computer system, comprising:

a central processing unit (“

CPU”

);

a system controller coupled to the CPU, the system controller having an input port and an output port;

an input device coupled to the CPU through the system controller;

an output device coupled to the CPU through the system controller;

a storage device coupled to the CPU through the system controller;

a plurality of memory modules, each of the memory modules comprising;

a plurality of memory devices; and

a memory hub comprising;

a link interface receiving memory requests for access to memory cells in at least one of the memory devices;

a memory device interface coupled to the memory devices, the memory device interface being operable to transfer memory requests to the memory devices for access to memory cells in at least one of the memory devices and to receive data responsive to at least some of the memory requests;

a prefetch circuit coupled to the link interface to receive memory requests from the link interface and coupled to the memory device interface to receive data from the memory cells, the prefetch circuit operable to predict addresses that are likely to be accessed in the memory devices based on the memory requests and generate prefetch suggestions indicative of the predicted addresses to prefetch data from memory cells, the prefetch circuit further operable to store the data that are prefetched and transfer the prefetched data to the link interface; and

a memory sequencer coupled to the link interface, the memory device interface and the prefetch circuit, the memory sequencer operable to transfer memory requests received from the link interface to the prefetch circuit to determine if the data corresponding to the memory requests are stored in the prefetch circuit, the memory sequencer further being operable to transfer memory requests received from the link interface to the memory device interface to fetch the data corresponding to the memory requests if the data are not stored, in the prefetch circuits, the memory sequencer further operable to generate prefetch requests responsive to the prefetch suggestions received from the prefetch circuit to fetch data corresponding to the prefetch suggestions.

43. The computer system of claim 42 wherein the prefetch circuit is operable to detect a pattern from which addresses to memory requests likely to be accessed are predicted, and operable to generate prefetch suggestions indicative of addresses corresponding to the predicted memory requests.

44. The computer system of claim 43 wherein the prefetch circuit is further operable to group the predicted memory request addresses into a plurality of sets corresponding to respective strides, and to cause the prefetched data received from the memory cells to be stored into a plurality of sections each corresponding to a respective stride.

45. The computer system of claim 43 wherein the prefetch circuit is further operable to selectively enable prefetching data based on the nature of the memory requests received from the link interface.

46. The computer system of claim 45 wherein the prefetch circuit is configured to selectively enable prefetching based on a percentage of memory requests for read data from the stored prefetch data compared to read data from the memory cells.

47. The computer system of claim 42 wherein the prefetch circuit comprises a plurality of prefetch buffers coupled to the memory device interface for receiving and storing prefetched data from memory cells being accessed based on the prefetch suggestions.

48. The computer system of claim 47 wherein the plurality of prefetch buffers comprises a single static random access memory device partitioned into a plurality of sections corresponding a plurality of strides.

49. The computer system of claim 47 wherein the plurality of prefetch buffers comprises a plurality of registers that are enabled and partitioned according to a plurality of respective strides.

50. The computer system of claim 47 wherein the prefetch circuit comprises a data read control circuit coupled to the memory device interface, the link interface, and the plurality of prefetch buffers, the data read control circuit operable to determine from the memory requests received from the link interface if the data corresponding to the memory requests are stored in the plurality of prefetch buffers, the data read control circuit further operable to transfer data from the plurality of prefetch buffers if the requested data are stored in the plurality of prefetch buffers and to transfer data from the memory device interface if the data are stored in the memory cells.

51. The computer system of claim 50 wherein the data read control circuit comprises a tag logic unit coupled to the link interface and the plurality of prefetched buffers, the tag logic unit operable to store addresses of the prefetched data stored in the plurality of prefetch buffers, the tag logic unit further operable to receive memory requests from the link interface, compare the addresses of the received memory requests to the addresses of the stored prefetched data, and generate a hit control signal indicative of whether an address match was determined.

52. The computer system of claim 51 wherein the tag logic unit is further coupled the memory sequencer to which the hit control signal is applied, and wherein the memory sequencer is prevented from transferring a memory request to the memory device interface responsive to receiving an active hit control signal.

53. The computer system of claim 50 wherein the data read control circuit comprises a multiplexer having data inputs coupled to the plurality of prefetch buffers, to the tag logic unit and to the memory device interface, and a data output coupled to the link interface, the multiplexer operable to transfer the data input from the plurality of prefetch buffers to the data output responsive to an active hit control signal received from the tag logic unit, and to transfer the data input from the memory device interface to the data output responsive to an inactive hit control signal received from the tag logic unit.

54. The computer system of claim 42 wherein the memory sequencer is operable to generate and transfer prefetch requests to the memory device interface only when memory requests are not being transferred from the link interface to the memory sequencer.

55. The computer system of claim 42 wherein the prefetch circuit is further operable to prefetch data from memory cells that are currently accessed such that the act of prefetching data does not require the selected memory cells to be precharged.

56. The computer system of claim 42 wherein the link interface comprises an optical input/output port.

57. A computer system, comprising:

a central processing unit (“

CPU”

);

a system controller coupled to the CPU, the system controller having an input port and an output port;

an input device coupled to the CPU through the system controller;

an output device coupled to the CPU through the system controller;

a storage device coupled to the CPU through the system controller;

a plurality of memory modules, each of the memory modules comprising;

a plurality of memory devices; and

a system for prefetching data comprising;

a link interface receiving memory requests for access to memory cells in at least one of the memory devices;

a memory device interface coupled to the memory devices, the memory device interface being operable to transfer memory requests to the memory devices for access to memory cells in at least one of the memory devices and to receive read data responsive to at least some of the memory requests; and

a prefetch circuit coupled to the link interface to receive memory requests from the link interface and coupled to the memory device interface to receive data from the memory cells, the prefetch circuit operable to predict addresses that are likely to be accessed in the memory devices based on the memory requests and to prefetch and store data from memory cells according to the predicted addresses, the prefetch circuit further operable to provide the prefetched data to the link interface responsive to subsequent memory requests, the prefetch circuit comprising a single static random access memory device partitioned into a plurality of sections corresponding a plurality of strides and being coupled to the memory device interface for receiving and storing prefetched data from memory cells being accessed based on the predicted addresses.

58. A computer system, comprising:

a central processing unit (“

CPU”

);

a system controller coupled to the CPU, the system controller having an input port and an output port;

an input device coupled to the CPU through the system controller;

an output device coupled to the CPU through the system controller;

a storage device coupled to the CPU through the system controller;

a plurality of memory modules, each of the memory modules comprising;

a plurality of memory devices; and

a system for prefetching data comprising;

a link interface receiving memory requests for access to memory cells in at least one of the memory devices;

a memory device interface coupled to the memory devices, the memory device interface being operable to transfer memory requests to the memory devices for access to memory cells in at least one of the memory devices and to receive read data responsive to at least some of the memory requests; and

a prefetch circuit coupled to the link interface to receive memory requests from the link interface and coupled to the memory device interface to receive data from the memory cells, the prefetch circuit operable to predict addresses that are likely to be accessed in the memory devices based on the memory requests and to prefetch and store data from memory cells according to the predicted addresses, the prefetch circuit further operable to provide the prefetched data to the link interface responsive to subsequent memory requests, the prefetch circuit further comprising;

a plurality of prefetch buffers coupled to the memory device interface for receiving and storing prefetched data from memory cells being accessed based on the predicted addresses; and

a data read control circuit coupled to the, memory device interface, the link interface, and the plurality of prefetch buffers, the data read control circuit operable to determine from the memory requests received from the link interface if the data corresponding to the memory requests are stored in the plurality of prefetch buffers, the data read control circuit further operable to transfer data from the plurality of prefetch buffers if the requested data are stored in the plurality of prefetch buffers and to transfer data from the memory device interface if the data are stored in the memory cells.

59. The computer system of claim 58 wherein the data read control circuit comprises a tag logic unit coupled to the link interface and the plurality of prefetched buffers, the tag logic unit operable to store addresses of the prefetched data stored in the plurality of prefetch buffers, the tag logic unit further operable to receive memory requests from the link interface, compare the addresses of the received memory requests to the addresses of the stored prefetched data, and generate a hit control signal indicative of whether an address match was determined.

60. The computer system of claim 58 wherein the data read control circuit comprises a multiplexer having data inputs coupled to the plurality of prefetch buffers, to the tag logic unit and to the memory device interface, and a data output coupled to the link interface, the multiplexer operable to transfer the data input from the plurality of prefetch buffers to the data output responsive to an active hit control signal received from the tag logic unit, and to transfer the data input from the memory device interface to the data output responsive to an inactive hit control signal received from the tag logic unit.

61. A method of prefetching data in a memory system comprising:

receiving memory requests for access to memory cells in a plurality of memory devices;

coupling the memory requests to the memory devices, wherein at least some of the memory requests being memory requests to read data;

receiving read data responsive to the read memory requests;

prefetching data from the memory devices that are likely to be accessed in the memory devices based on the received memory requests and storing the prefetched data;

transferring the prefetched data responsive to subsequent memory requests;

dividing the stored prefetched data into a plurality of sections each corresponding to a respective stride; and

storing the prefetched data from the memory devices indicative of the predicted addresses in the section corresponding to the respective stride.

62. The method of claim 61 further comprising:

storing prefetch addresses corresponding to the stored prefetched data;

receiving memory request addresses corresponding to subsequent memory requests;

comparing each received memory request address to the prefetch addresses; and

determining that the requested read data are stored as prefetched data in the event of an address match.

63. The method of claim 62 further comprising:

transferring read data stored as prefetched data responsive to determining that the requested read data are stored as prefetched data; and

transferring read data from the memory devices responsive to determining that the requested read data are not stored as prefetched data.

64. The method of claim 61 further comprising prefetching data from memory cells that are currently accessed such that the prefetching does not require the selected memory cells to be precharged.

65. The method of claim 61 wherein prefetching data from the memory devices comprises prefetching data only when the memory requests are not being received.

66. The method of claim 61 further comprising selectively enabling prefetching based on the nature of the received memory requests.

67. The method of claim 61 wherein the act of receiving memory requests for access to memory cells in a plurality of memory devices comprises receiving optical signals corresponding to the memory requests.

68. A method of reading data in a memory hub comprising:

receiving memory requests for access to a memory device;

coupling the memory requests to the memory device responsive to the received memory request, at least some of the memory requests being memory requests to read data;

receiving read data responsive to the read memory requests;

predicting addresses that are likely to be accessed in the memory device based on the read memory requests;

generating prefetch requests indicative of the predicted addresses;

prefetching and storing the read data from the memory device responsive to the prefetch requests;

determining from a read memory request if the requested read data are stored as prefetched data;

transferring the prefetched data if a determination has been made;

transferring data from the memory device if a determination has not been made;

grouping the predicted addresses into a plurality of sets corresponding to respective strides;

dividing the stored prefetched data into a plurality of sections each corresponding to a respective stride; and

storing the prefetched data from the memory devices indicative of the predicted addresses in the section corresponding to the stride containing the predicted address from which the data was read.

69. The method of claim 68 further comprising:

storing prefetch addresses corresponding to the stored prefetched data;

receiving memory request addresses corresponding to subsequent memory requests;

comparing each received memory request address to the prefetch addresses; and

determining that the requested read data are stored as prefetched data in the event of an address match.

70. The method of claim 68 further comprising prefetching data from memory cells that are currently accessed such that the prefetching does not require the selected memory cells to be precharged.

71. The method of claim 68 wherein prefetching and storing the read data from the memory device responsive to the prefetch requests comprise prefetching data only when the memory requests are not being received.

72. The method of claim 68 further comprising selectively enabling prefetching based on the nature of the received memory requests.

73. The method of claim 68 wherein the act of receiving memory requests for access to memory cells in a plurality of memory devices comprises receiving optical signals corresponding to the memory requests.