Value-based memory coherence support

• US 7,412,567 B2
• Filed: 04/28/2006
• Issued: 08/12/2008
• Est. Priority Date: 04/28/2006
• Status: Active Grant

• Current Assignee: Oracle America, Inc. (Oracle Corporation)
• Original Assignee: Sun Microsystems Incorporated (Oracle Corporation)
• Inventors: Cypher, Robert E., Chaudhry, Shailender, Hagersten, Erik E., Landin, Anders, Loewenstein, Paul N., Zeffer, Hakan E., Radovic, Zoran
• Primary Examiner(s): Verbrugge; Kevin
• Application Number:
  US11/413,243
• Publication Number:
  US 20070255907A1
• Time in Patent Office: 837 Days
• Field of Search: None
• US Class Current: 711/141
• CPC Class Codes: G06F 12/0808 with cache invalidating means G06F12/0815 takes precedence
• CPC Class Codes: G06F 12/0815 Cache consistency protocols
• CPC Class Codes: G06F 12/0822 Copy directories local copy tags for implementing a bus snooping protocol G06F12/0831
• CPC Class Codes: G06F 12/0897 with two or more cache hierarchy levels with multilevel cache hierarchies G06F12/0811

Abstract

In one embodiment, a processor comprises a coherence trap unit and a trap logic coupled to the coherence trap unit. The coherence trap unit is also coupled to receive data accessed in response to the processor executing a memory operation. The coherence trap unit is configured to detect that the data matches a designated value indicating that a coherence trap is to be initiated to coherently perform the memory operation. The trap logic is configured to trap to a designated software routine responsive to the coherence trap unit detecting the designated value. In some embodiments, a cache tag in a cache may track whether or not the corresponding cache line has the designated value, and the cache tag may be used to trigger a trap in response to an access to the corresponding cache line.

Claims

1. A processor comprising:

a store queue configured to store addresses to be written in response to stores and store data, and wherein the store queue is coupled to a load data path that delivers load data to a destination of the load, the store queue coupled to the load data path to forward store data for a matching load address;

a coherence trap unit coupled to the load data path prior to a point at which the store data from the store queue is merged with other data to receive memory data accessed in response to the processor executing a load memory operation, wherein the coherence trap unit is configured to detect whether the memory data matches a designated value indicating that a coherence trap is to be initiated to coherently perform the memory operation; and

trap logic coupled to the coherence trap unit and configured to trap to a designated software routine responsive to the coherence trap unit detecting the designated value.

2. The processor as recited in claim 1 wherein the coherence trap unit comprises a register that is programmable with the designated value.

3. The processor as recited in claim 1 wherein, for a store memory access, the coherence trap unit is configured to detect whether data prior to update by the store is the designated value.

4. The processor as recited in claim 1 wherein the coherence trap unit is configured to hash the memory data and compare the hash result data to the designated value.

5. A cache comprising:

a data memory configured to store a plurality of cache lines of data;

a tag memory configured to store a plurality of cache tags corresponding to the plurality of cache lines, wherein each of the plurality of cache tags comprises an indication of whether or not the corresponding cache line is storing one or more data values that match a designated value, the designated value indicating that an access to the corresponding cache line causes a trap to software to ensure cache coherence; and

a control unit coupled to the data memory and the tag memory, wherein the control unit is configured to detect the indication responsive to a cache access and to signal a processor coupled to the cache to cause the trap.

6. The cache as recited in claim 5 further comprising a register programmable with the designated value, wherein the register is coupled to a comparator to compare the data during a fill of a cache line to determine the indication for the corresponding cache tag.

7. The cache as recited in claim 5 further comprising a register programmable to indicate that a given cache line contains the designated value but is not indicating the trap to software.

8. The cache as recited in claim 7 wherein, during a fill of a given cache line, the control unit is configured not to set the indication in the corresponding cache tag to indicate the trap responsive to the register, even if the data loaded into the cache line includes the designated value.

9. The cache as recited in claim 8 wherein the register is programmable with a tag address, and wherein the register contents are compared to the address of the access.

10. The cache as recited in claim 5 further comprising a register programmable to indicate that an access to a given cache line is to cause a trap even if the cache line does not contain the designated value.

11. The cache as recited in claim 10 wherein, during a fill of a given cache line, the control unit is configured to set the indication in the corresponding cache tag to indicate the trap responsive to the register, even if the data loaded into the cache line does not include the designated value.

12. The cache as recited in claim 11 wherein the register is programmable with a tag address, and wherein the register contents are compared to the address of the access.

13. A method comprising:

detecting that data corresponding to a memory operation has a designated value that indicates a trap to software to ensure coherence is to be performed;

trapping to the software responsive to the detecting; and

programming a register to indicate that a given cache line contains the designated value but is not to cause a trap.

14. The method as recited in claim 13 further comprising programming the designated value into a register.

15. The method as recited in claim 13 wherein the detecting comprises comparing data from a load data path to the designated value.

16. The method as recited in claim 13 further comprising programming a register to indicate that a given cache line is to cause the trap even if the designated value is not detected.

17. A processor comprising:

trap detection logic configured to detect whether coherence activity is necessary to obtain a coherent copy of data accessed by a memory operation being performed by the processor, wherein the trap detection logic is configured to detect whether coherence activity is necessary at a granularity that is no larger than a cache line, and wherein the trap detection logic is configured to detect whether coherence activity is necessary responsive to cache tag data corresponding to a cache line that includes the data accessed by the memory operation; and

trap logic coupled to the trap detection logic and configured to trap to a designated software routine responsive to the trap detection logic detecting that the coherence activity is necessary.

18. The processor as recited in claim 17 wherein the trap detection logic is configured to compare data accessed by the memory operation to a designated value indicating a coherence trap to detect whether coherence activity is necessary.

19. The processor as recited in claim 17 wherein the cache tag data is generated by comparing the cache data to a designated value indicating a coherence trap to detect whether coherence activity is necessary.