Memory arbitration system and method having an arbitration packet protocol

• US 7,412,571 B2
• Filed: 03/29/2007
• Issued: 08/12/2008
• Est. Priority Date: 03/24/2004
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Jeddeloh, Joseph M., James, Ralph
• Primary Examiner(s): BRAGDON, REGINALD GLENWOOD
• Application Number:
  US11/731,122
• Publication Number:
  US 20070180171A1
• Time in Patent Office: 502 Days
• Field of Search: None
• US Class Current: 711/151
• CPC Class Codes: G06F 13/1605 based on arbitration arbitration in handling access to a common bus or bus system G06F13/36
• CPC Class Codes: G06F 13/1642 with request queuing
• CPC Class Codes: G06F 13/1684 using multiple buses

Abstract

A memory hub and method for transmitting a read response on a data path of a memory hub interposed between a transmitting memory hub and a receiving memory hub. An arbitration packet including data indicative of a data path configuration for an associated read response is received at the memory hub. The arbitration packet is decoded, and the data path is configured in accordance with the data of the arbitration packet. The associated read response is received at the memory hub and the associated read response is coupled to the configured data path for transmitting the same to the receiving memory hub.

Claims

1. A memory hub coupled to at least one memory device, the memory hub comprising:

remote and local input nodes;

an output node;

a configurable data path coupled to the remote and local input nodes and further coupled to the output node, the configurable data path operable to couple at least one read response received by the remote and local input nodes to the output node; and

an arbitration control circuit coupled to the configurable data path, the output node, and the remote and local input nodes, the arbitration control circuit operable to generate an arbitration packet that includes data indicative of a data path configuration for a local read response received by the local input node and operable to provide the arbitration packet to the output node prior to providing the associated read response to the output node, the arbitration control circuit further operable to configure the configurable data path in accordance with data included in a downstream arbitration packet received by the remote input node in preparation of coupling an associated downstream read response to the output node.

2. The memory hub of claim 1 wherein the configurable data path comprises:

a multiplexer having an output coupled to the output node and a control node coupled to the arbitration control circuit;

a bypass data path coupled to the remote input node and a first input of the multiplexer;

a local queue having an input coupled to the local input node and further having an output coupled to a second input of the multiplexer; and

a remote queue having an input coupled to the remote input node and further having an output coupled to a third input of the multiplexer, the arbitration control circuit operable to generate a control signal for the multiplexer to selectively couple the bypass data path, local queue, or remote queue to the output node.

3. The memory hub of claim 2 wherein the arbitration control circuit is operable to store the local read response received by the local input node in the local queue and the downstream read response in the remote queue until the output node is ready to receive the respective read response.

4. The memory hub of claim 1 wherein the arbitration control circuit is operable to determine whether a local data path of the memory hub coupled to the local input node is idle, and in the event that the local data path is idle, operable to generate the arbitration packet for the local read response received by the local input node.

5. The memory hub of claim 4 wherein the arbitration packet and the local read response of the local data path is selected for transmission to the output node responsive to a predetermined arbitration scheme.

6. The memory hub of claim 1 wherein the arbitration control circuit is further operable to generate data for the arbitration packet that is used to distinguish the arbitration packet from a read response.

7. The memory hub of claim 6 wherein the arbitration packet includes a plurality of 8-bit bytes of information, wherein the plurality of 8-bit bytes of information includes one byte of data used to distinguish the arbitration packet from the read response.

8. A memory hub, comprising:

a bypass data path coupled between an input node and an output node on which read responses are applied in response to being enabled; and

an arbitration control circuit coupled to the bypass data path operable to receive an arbitration packet from a downstream memory hub and enable the bypass data path to receive a read response from the downstream memory hub responsive to the received arbitration packet, the arbitration packet including a data path field having activation data to enable the bypass data path of an upstream memory hub, the arbitration control circuit further operable to query an upstream memory hub to enable a bypass data path of the upstream memory hub to receive the read response from the downstream memory hub when the upstream memory hub is not busy.

9. The memory hub of claim 8, further comprising:

a multiplexer having an output coupled to the output node and a control node coupled to the arbitration control circuit, the multiplexer further having a first input coupled to the bypass data path;

a local queue having an input coupled to a local input node and further having an output coupled to a second input of the multiplexer; and

a remote queue having an input coupled to the input node and further having an output coupled to a third input of the multiplexer, the arbitration control circuit operable to generate a control signal for the multiplexer to selectively couple the bypass data path, local queue, or remote queue to the output node.

10. The memory hub of claim 9 wherein the arbitration control circuit is operable to store the read response received from the downstream memory hub in the remote queue when the upstream memory hub is busy.

11. The memory hub of claim 10 wherein the arbitration control circuit is operable to store read data from a memory device coupled to the memory hub in the local queue, and generate an arbitration packet in response to the received read data when the upstream memory hub is not busy.

12. The memory hub of claim 8, wherein the arbitration packet includes a plurality of 8-bit bytes of data, wherein the plurality of 8-bit bytes includes one byte of data used to distinguish the arbitration packet from the read response.

13. A memory module, comprising:

a plurality of memory devices; and

a memory hub coupled to the memory devices through a memory device bus to access the memory devices, the memory hub comprising;

remote and local input nodes, the local input node coupled to the memory device bus;

an output node;

a configurable data path coupled to the remote and local input nodes and further coupled to the output node, the configurable data path operable to couple at least one read response received by the remote and local input nodes to the output node; and

an arbitration control circuit coupled to the configurable data path, the output node, and the remote and local input nodes, the arbitration control circuit operable to generate an arbitration packet that includes data indicative of a data path configuration for a local read response received by the local input node and operable to provide the arbitration packet to the output node prior to providing the read response to the output node, the arbitration control circuit further operable to configure the configurable data path in accordance with data included in a downstream arbitration packet received by the remote input node in preparation of coupling an associated downstream read response to the output node.

14. The memory module of claim 13 wherein the configurable data path of the memory hub comprises:

a multiplexer having an output coupled to the output node and a control node coupled to the arbitration control circuit;

a bypass data path coupled to the remote input node and a first input of the multiplexer;

a local queue having an input coupled to the local input node and further having an output coupled to a second input of the multiplexer; and

a remote queue having an input coupled to the remote input node and further having an output coupled to a third input of the multiplexer, the arbitration control circuit operable to generate a control signal for the multiplexer to selectively couple the bypass data path, local queue, or remote queue to the output node.

15. The memory module of claim 14 wherein the arbitration control circuit is operable to store the local read response received by the local input node in the local queue and the downstream read response in the remote queue until the output node is ready to receive the respective read response.

16. The memory module of claim 13 wherein the arbitration control circuit is operable to determine whether a local data path of the memory hub coupled to the local input node is idle, and in the event that the local data path is idle, operable to generate the arbitration packet for the local read response received by the local input node.

17. The memory module of claim 13 wherein the arbitration packet includes a plurality of 8-bit bytes of information, wherein the plurality of 8-bit bytes of information includes one byte of data used to distinguish the arbitration packet from the read response.

18. A memory module, comprising:

a plurality of memory devices; and

a memory hub coupled to the memory devices through a memory device bus to access the memory devices, the memory hub comprising;

a bypass data path coupled between an input node and an output node on which read responses are applied in response to being enabled; and

an arbitration control circuit coupled to the bypass data path operable to receive an arbitration packet from a downstream memory hub and enable the bypass data path to receive a read response from the downstream memory hub responsive to the received arbitration packet, the arbitration packet including a data path field having activation data to enable the bypass data path of an upstream memory hub, the arbitration control circuit further operable to query an upstream memory hub to enable a bypass data path of the upstream memory hub to receive the read response from the downstream memory hub when the upstream memory hub is not busy.

19. The memory module of claim 18 wherein the memory hub further comprises:

a multiplexer having an output coupled to the output node and a control node coupled to the arbitration control circuit, the multiplexer further having a first input coupled to the bypass data path;

a local queue having an input coupled to a local input node and further having an output coupled to a second input of the multiplexer; and

a remote queue having an input coupled to the input node and further having an output coupled to a third input of the multiplexer, the arbitration control circuit operable to generate a control signal for the multiplexer to selectively couple the bypass data path, local queue, or remote queue to the output node.

20. The memory module of claim 19 wherein the arbitration control circuit is operable to store the memory response received from the downstream memory hub in the remote queue when the upstream memory hub is busy.

21. The memory module of claim 20 wherein the arbitration control circuit is operable to store read data from a memory device coupled to the memory hub in the local queue, and generate an arbitration packet in response to the received read data when the upstream memory hub is not busy.

22. The memory module of claim 18, wherein the arbitration packet includes a plurality of 8-bit bytes of data, wherein the plurality of 8-bit bytes includes one byte of data used to distinguish the arbitration packet from the read response.

23. A memory system having a plurality of memory modules, each memory module including a memory hub, the memory system comprising:

a memory bus;

a first memory hub having a first input terminal and a first output terminal coupled to the memory bus, the first memory hub including a first arbitration control circuit operable to generate a first arbitration packet including information to configure a data path responsive to retrieving read data from a memory device coupled to the first memory hub and provide the first arbitration packet to the memory bus through the first output terminal prior to providing the read data; and

a second memory hub having a second input terminal and a second output terminal coupled to the memory bus, the second memory hub including a second arbitration control circuit configured to receive the first arbitration packet, the second arbitration control circuit operable to configure the data path in accordance with the information in the first arbitration packet, the second arbitration control circuit further operable to generate a second arbitration packet indicative of either the information of the first arbitration packet or read data retrieved from a memory device coupled to the second memory hub, and provide the second arbitration packet to the output terminal prior to providing the corresponding read data, each of the arbitration control circuits of the first and second memory hubs operable to store the read data and the read response when the first and second output terminals are busy.

24. The memory system of claim 23 wherein each of the arbitration packets comprises a data structure having a command code field that identifies the data structure as an arbitration packet that is distinguishable from a read response, and an address field that includes data to identify the particular hub to which the arbitration packet or the read response is directed.

25. The memory system of claim 23 wherein each of the arbitration packets includes a plurality of 8-bit bytes of information, wherein the plurality of 8-bit bytes of information includes one byte of data used to distinguish the arbitration packet from the read response.

26. A memory system, comprising:

a plurality of memory modules, each having a memory hub configured to be in communication with each other, each of the memory hubs operable to propagate memory requests downstream and read responses upstream from one memory hub to another memory hub towards a memory controller;

a responding memory module having a responding memory hub, the responding memory hub comprising;

a local input node configured to receive read data from a memory device coupled to the responding memory hub by a local data path to generate a read response that includes the read data;

a remote input node configured to receive a downstream arbitration packet and associated read response from a downstream memory hub on a memory bus; and

an arbitration control circuit coupled to the local input node and the remote input node, the arbitration control circuit operable to determine whether the local data path of the responding memory hub is idle, and in the event that the local data path is idle, operable to encode a data path configuration in an arbitration packet to transmit the read response received by the local input node to transmit towards the memory controller, the arbitration control circuit further operable to decode the downstream arbitration packet received by the remote input node to generate an upstream arbitration packet encoding a data path to transmit the downstream read response to the memory controller.

27. The memory system of claim 26 wherein each of the arbitration packets comprises a command code field that identifies its data structure as an arbitration packet that is distinguishable from the read response, and an address field that includes data to identify the particular hub to which the arbitration packet or the read response is directed.

28. The memory system of claim 26 wherein each of the arbitration packets is transmitted prior to transmitting the associated read response.

29. A memory hub coupled to at least one memory device, the memory hub comprising:

remote and local input nodes;

an output node;

a configurable data path coupled to the remote and local input nodes and further coupled to the output node, the configurable data path operable to couple at least one of a read response coupled through the remote and local input nodes to the output node; and

an arbitration control circuit coupled to the configurable data path, the output node, and the remote input node, the arbitration control circuit operable to generate an arbitration packet for an associated read response coupled through the local input node and further operable to generate data for the arbitration packet that is used to distinguish the arbitration packet from the associated read response, the arbitration packet including data indicative of a data path configuration for the associated read response, the arbitration control circuit further operable to configure the configurable data path in accordance with the data included with an arbitration packet coupled thorough the remote input node in preparation of coupling an associated read response coupled through the remote input node to the output node.

30. The memory hub of claim 29 wherein the configurable data path comprises:

a multiplexer having an output coupled to the output node and a control node coupled to the arbitration control circuit;

a bypass data path coupled to the remote input node and a first input of the multiplexer;

a local queue having an input coupled to the local input node and further having an output coupled to a second input of the multiplexer; and

a remote queue having an input coupled to the remote input node and further having an output coupled to a third input of the multiplexer, the arbitration control circuit operable to generate a control signal for the multiplexer to selectively couple the bypass data path, local queue, or remote queue to the output node.

31. A memory hub, comprising:

a bypass data path coupled between an input node and an output node on which read responses are coupled therebetween in response to being enabled;

an arbitration control circuit coupled to the bypass data path operable to generate an arbitration packet in response to retrieving read data from a memory device coupled to the memory hub, the arbitration packet having a data path field including activation data to enable a bypass data path of an upstream memory hub, the arbitration control circuit further operable to receive an arbitration packet from a downstream memory hub and enable the bypass data path to couple a read response received therefrom from the input node to the output node;

a multiplexer having an output coupled to the output node and a control node coupled to the arbitration control circuit, the multiplexer further having a first input coupled to the bypass data path;

a local queue having an input coupled to a local input node and further having an output coupled to a second input of the multiplexer; and

a remote queue having an input coupled to the input node and further having an output coupled to a third input of the multiplexer, the arbitration control circuit operable to generate a control signal for the multiplexer to selectively couple the bypass data path, local queue, or remote queue to the output node.

32. A memory hub coupled to at least one memory device, the memory hub comprising:

remote and local input nodes;

an output node;

a configurable data path coupled to the remote and local input nodes and further coupled to the output node, the configurable data path operable to couple at least one read response received by the remote and local input nodes to the output node; and

an arbitration control circuit coupled to the configurable data path, the output node, and the remote and local input nodes, the arbitration control circuit operable to generate an arbitration packet that includes data indicative of a data path configuration for a local read response received by the local input node and operable to determine whether a local data path of the memory hub coupled to the local input node is idle, and in the event that the local data path is idle, operable to generate the arbitration packet for the local read response received by the local input node, the arbitration control circuit further operable to configure the configurable data path in accordance with data included in a downstream arbitration packet received by the remote input node in preparation of coupling an associated downstream read response to the output node.