Network processor system on chip with bridge coupling protocol converting multiprocessor macro core local bus to peripheral interfaces coupled system bus

• US 7,412,588 B2
• Filed: 01/30/2004
• Issued: 08/12/2008
• Est. Priority Date: 07/25/2003
• Status: Active Grant

• Current Assignee: Microsoft Technology Licensing LLC (Microsoft Corporation)
• Original Assignee: International Business Machines Corporation
• Inventors: Salapura, Valentina, Gregurick, Victor L., Georgiou, Christos J., Nair, Indira
• Primary Examiner(s): Kim; Kenneth S
• Application Number:
  US10/768,828
• Publication Number:
  US 20050021874A1
• Time in Patent Office: 1,656 Days
• Field of Search: None
• US Class Current: 712/33
• CPC Class Codes: G06F 15/167 using a common memory, e.g. mailbox
• CPC Class Codes: G06F 15/7825 Globally asynchronous, locally synchronous, e.g. network on chip
• CPC Class Codes: G06F 15/7832 on one IC chip (single chip microprocessors)
• CPC Class Codes: G06F 15/7842 on one IC chip (single chip microcontrollers)
• CPC Class Codes: H04L 49/109 Integrated on microchip, e.g. switch-on-chip
• CPC Class Codes: H04L 49/602 Multilayer or multiprotocol switching, e.g. IP switching

Abstract

A network processor includes a system-onchip (SoC) macro core and functions as a single chip protocol converter that receives packets generating according to a first protocol type and processes the packets to implement protocol conversion and generates converted packets of a second protocol type for output thereof, the process of protocol conversion being performed entirely within the SoC macro core. The process of protocol conversion contained within the SoC macro core does not require the processing resources of a host system. The system-on chip macro core includes a bridge device for coupling a local bus in the protocol converting multiprocessor SoC macro core local bus to peripheral interfaces coupled to a system bus.

Claims

1. A System-on-Chip (SoC) protocol converter integrated circuit (IC) comprising:

an embedded System-on-Chip (SoC) core for protocol conversion, a microprocessor; and

,

a local system communications bus, said embedded System-on-Chip (SoC) core for protocol conversion comprising;

a processor based sub-system including two or more processor cluster assemblies, each processor cluster assembly comprising;

one or more sub processing cores each capable of performing operations to implement protocol conversion capability;

a local storage device associated with said one or more sub processing cores in said processor cluster assembly for storing at least one of data and instructions in each processor cluster assembly; and

,

a first local interconnect means residing in each said processor cluster assembly for enabling communication of instructions and data between said local storage device and said one or more sub processing cores;

one or more interface devices enabling receipt and transmission of communications packets according to one or more communications protocols; and

a second local interconnect means residing in said embedded SoC core for enabling communication between either two or more processor clusters and said one or more interface devices or, two or more sub processor cores within a processor cluster and said one or more interface devices; and

,

a bridging device for enabling send and receive data communications between said second local interconnect means of said embedded SoC core for protocol conversion and said local system communications bus of said SoC protocol converter IC,

wherein an interface device is configurable as an inbound network interface adapted for receiving packets generated according to a first protocol type for forwarding to a processor cluster assembly or sub processing core within a processor cluster assembly programmed for processing said packets to implement protocol conversion and, is configurable as an outbound interface device for outputting converted packets of a second protocol type, whereby protocol conversion processing is performed entirely within the SoC integrated circuit chip.

2. The SoC protocol converter IC devices as claimed in claim 1, wherein said one or more configurable interface devices are capable of receiving communications according to a network communications protocol including one or more from the group comprising:

Fibre Channel, Gb Ethernet, Infiniband, iSCSI, FC-IP, TCP/IP, IP, MPLS, VoDSL, CAN and SAMBA.

3. The SoC protocol converter IC as claimed in claim 1, wherein said one or more configurable interface devices include one or more from the group comprising:

a programmable Media Access Control interface device (MAC), and a protocol interface accelerator device for receiving packets of a particular protocol.

4. The SoC protocol converter IC as claimed in claim 3, wherein said one or more processor cluster assemblies, corresponding local storage devices, first and second local interconnect means and said one or more interface devices cooperatively enable packet resizing and reformatting needed for conversion between the first and seconds protocols, said single chip protocol converter design additionally adapted to enable conversion of received packets between different version levels of a single protocol type.

5. The SoC protocol converter IC as claimed in claim 1, whereby the received packet of a first type is partitioned to one or more sub processor cores of a processor cluster assembly, with each sub processor core running the same set of instructions and being paired with a specific protocol process.

6. The SoC protocol converter IC as claimed in claim 1, wherein the received instructions for protocol conversion are comprised entirely within a processor cluster assembly, said processing including partitioning of the protocol operations for handling by different resources on the single chip protocol converter IC.

7. The SoC protocol converter IC as claimed in claim 1, wherein said second local interconnect means includes a crossbar switch.

8. The SoC protocol converter IC as claimed in claim 1, further including a means for adapting a single chip protocol converter design to perform one or more functions related to protocol conversion.

9. The SoC protocol converter IC as claimed in claim 1, wherein the process of protocol conversion is contained within the embedded SoC protocol conversion macro core.

10. The SoC protocol converter IC as claimed in claim 1, wherein the single chip protocol converter IC comprises components for protocol conversion processing including a local embedded memory storage element for receiving a communications packet to be converted from said one or more interface devices, and storing a protocol conversion application program, control information, and data used by the application program.

11. The SoC protocol converter IC as claimed in claim 10, wherein one or more sub processor cores within the processor cluster assembly performs one or more tasks including:

memory control, packet dispatch, header and trailer generation or manipulation, payload resizing, and packet collection to convert a given packet or packets of a first protocol type to a second packet or packets of a second protocol type, whereas the packet or packets of a second protocol type are transferred to a second outbound network interface device within the protocol converter chip for transmission.