Utilizing multiple bitstreams to avoid localized defects in partially defective programmable integrated circuits

• US 7,412,635 B1
• Filed: 10/01/2004
• Issued: 08/12/2008
• Est. Priority Date: 10/01/2004
• Status: Active Grant

• Current Assignee: Xilinx, Inc. (Advanced Micro Devices, Inc.)
• Original Assignee: Xilinx, Inc. (Advanced Micro Devices, Inc.)
• Inventors: Trimberger, Stephen M.
• Primary Examiner(s): Louis-Jacques; Jacques
• Assistant Examiner(s): Merant; Guerrier
• Application Number:
  US10/956,986
• Time in Patent Office: 1,411 Days
• Field of Search: None
• US Class Current: 714/725
• CPC Class Codes: G01R 31/318516 Test of programmable logic devices [PLDs]

Abstract

Methods and structures utilizing multiple configuration bitstreams to program integrated circuits (ICs) such as programmable logic devices (PLDs), thereby enabling the utilization of partially defective ICs. A user design is implemented two or more times, preferably utilizing different programmable resources as much as possible in each configuration bitstream. The resulting configuration bitstreams are stored in a memory device such as a programmable read-only memory (PROM). Under the control of a configuration control circuit or device, the various bitstreams are sequentially loaded into a partially defective IC and tested using an automated testing procedure. When a bitstream is found that enables the design to function correctly in the programmed IC, i.e., that avoids the defective programmable resources in the IC, the automated testing procedure terminates, and the programmed IC begins to function according to the user design as determined by the last programmed bitstream.

Claims

1. A method of programming an integrated circuit (IC) to implement a design, comprising:

storing an initial configuration bitstream and a subsequent configuration bitstream, wherein the initial and subsequent configuration bitstreams are stored for programming programmable logic and programmable interconnect of the IC, and the initial and a subsequent configuration bitstreams are different and implement an equivalent function for the design;

programming the initial configuration bitstream into the IC and applying an automated testing procedure to the IC that is programmed with the initial configuration bitstream;

wherein the programming with the initial configuration bitstream is after the storing of both the initial and subsequent configuration bitstreams;

programming, when the IC fails to pass the automated testing procedure, the subsequent configuration bitstream into the IC and applying the automated testing procedure to the IC that is programmed with the subsequent configuration bitstream; and

when the IC passes the automated testing procedure, terminating the programming and allowing the IC to assume the equivalent function as determined by the subsequent configuration bitstream.

2. The method of claim 1, further comprising:

selecting, based on results of the automated testing procedure, one of a plurality of available configuration bitstreams to be the subsequent configuration bitstream.

3. The method of claim 1, wherein the applying the automated testing procedure comprises programming at least a portion of the IC with additional configuration data.

4. The method of claim 1, further comprising:

rejecting the IC as unsuitable for implementing the design when the IC is programmed with a final configuration bitstream and fails to pass the automated testing procedure.

5. The method of claim 1, further comprising:

providing a plurality of configuration bitstreams to be used by the automated configuration procedure, wherein each configuration bitstream implements the design in the IC, and each configuration bitstream utilizes a different set of programmable resources in the IC.

6. The method of claim 5, wherein at least one of the programmable resources in the IC is included in at least two of the sets of programmable resources.

7. The method of claim 5, wherein each of the programmable resources in the IC is excluded from at least one of the sets of programmable resources.

8. The method of claim 5, wherein each of the plurality of configuration bitstreams includes a common set of the programmable resources, and wherein logic implemented by the common set is implemented in the design using triple modular redundancy.

9. The method of claim 5, wherein each configuration bitstream enables the design to meet a common set of predetermined timing constraints when programmed into a fully functional IC.

10. The method of claim 5, further comprising:

storing the configuration bitstreams in a memory device; and

coupling the memory device to a configuration port of the IC.

11. The method of claim 5, further comprising:

providing a plurality of test data values, each test data value being associated with one of the configuration bitstreams.

12. The method of claim 11, wherein each test data value comprises data expected from the automated testing procedure when applied to a fully functional IC programmed with the associated configuration bitstream.

13. The method of claim 11, wherein the test data values comprise checksum values.

14. The method of claim 11, further comprising:

storing the configuration bitstreams and the test data values in a memory device; and

coupling the memory device to a configuration port of the IC.

15. The method of claim 1, wherein the applying the automated testing procedure comprises utilizing a configuration control circuit that forms a portion of the IC to control the automated testing procedure.

16. The method of claim 15, wherein the configuration control circuit utilizes JTAG INTEST to apply the automated testing procedure to the programmed IC.

17. The method of claim 1, wherein the applying the automated testing procedure comprises utilizing a configuration control circuit external to the IC to control the automated testing procedure.

18. The method of claim 17, wherein the configuration control circuit utilizes JTAG INTEST to apply the automated testing procedure to the programmed IC.

19. The method of claim 1, wherein the IC comprises a partially defective IC.

20. The method of claim 1, wherein the IC comprises a programmable logic device (PLD).

21. The method of claim 20, wherein the PLD comprises a field programmable gate array (FPGA).

22. The method of claim 1, wherein the programming the subsequent configuration bitstream into the IC comprises performing a partial reconfiguration of the IC.

23. A system, comprising:

means for storing an initial configuration bitstream and a subsequent configuration bitstream, wherein the initial and subsequent configuration bitstreams are stored for programming programmable logic and programmable interconnect of the IC, and the initial and a subsequent configuration bitstreams are different and implement an equivalent function for the design;

means for programming the initial configuration bitstream into an integrated circuit (IC) and programming, when the IC fails to pass an automated testing procedure, the subsequent configuration bitstream into the IC;

wherein the means for programming programs with the initial configuration bitstream after the storing of both the initial and subsequent configuration bitstreams;

means for applying the automated testing procedure to the IC; and

means for, when the IC passes the automated testing procedure, allowing the IC to assume the same predetermined function as determined by the subsequent configuration bitstream.

24. The structure of claim 23, wherein the structure comprises a programmable logic device (PLD).