System and method for tolerating communication lane failures

• US 7,412,642 B2
• Filed: 03/09/2005
• Issued: 08/12/2008
• Est. Priority Date: 03/09/2005
• Status: Active Grant

• Current Assignee: Oracle America, Inc. (Oracle Corporation)
• Original Assignee: Sun Microsystems Incorporated (Oracle Corporation)
• Inventors: Cypher, Robert E.
• Primary Examiner(s): Louis-Jacques; Jacques
• Assistant Examiner(s): CHAUDRY, MUJTABA M
• Application Number:
  US11/075,478
• Publication Number:
  US 20060212775A1
• Time in Patent Office: 1,252 Days
• Field of Search: 714/758, 714/776
• US Class Current: 714/776
• CPC Class Codes: H03M 13/09 Error detection only, e.g. using cyclic redundancy check [CRC] codes or single parity bit
• CPC Class Codes: H04L 1/0045 Arrangements at the receiver end
• CPC Class Codes: H04L 1/0057 Block codes H04L1/0061, H04L1/0064 take precedence
• CPC Class Codes: H04L 1/0063 Single parity check
• CPC Class Codes: H04L 1/18 Automatic repetition systems, e.g. Van Duuren systems
• CPC Class Codes: H04L 25/14 Channel dividing arrangements , i.e. in which a single bit stream is divided between several baseband channels and reassembled at the receiver

Abstract

A system for tolerating communication lane failures includes a transmitter configured to transmit a segment of data, an error detecting code, and redundant information. The system also includes a receiver coupled to the transmitter via a communication link including a plurality of bit lanes. Each bit of the segment of data may be conveyed to the receiver serially via respective single-bit lanes. The segment of data, the redundant information, and the error detecting code may be accumulated within the receiver over a plurality of clock cycles. The receiver may detect an error in the segment of data using the error detecting code. In addition, the receiver may, in response to detecting the error, regenerate the segment of data using the redundant information. Further, the receiver may determine whether a resulting regenerated bit, along with remaining bits, of the segment of data are correct using the error detecting code.

Claims

1. A system comprising:

a transmitter configured to transmit a segment of data, a cyclic redundancy code, and redundant information via separate bit lanes of a communication link including a plurality of bit lanes; and

a receiver coupled to the transmitter via the communication link, wherein each bit of the segment of data, and the cyclic redundancy code is conveyed from the transmitter to the receiver serially via a respective single-bit lane of the plurality of bit lanes;

wherein the segment of data, the redundant information, and the cyclic redundancy code are accumulated within the receiver over a plurality of clock cycles, wherein the cyclic redundancy code covers the segment of data accumulated over the plurality of clock cycles, and wherein the cyclic redundancy code is defined by a serial sequence of the bits of the segment of data conveyed upon each bit lane concatenated with the bits of the segment of data conveyed upon a next bit lane; and

wherein the receiver is configured to detect an error in the segment of data using the cyclic redundancy code, and in response to detecting the error to regenerate the segment of data using the redundant information, and to determine whether a resulting regenerated bit, along with remaining bits, of the segment of data is correct using the cyclic redundancy code.

2. The system as recited in claim 1, wherein the receiver is further configured to detect an error in the error detecting code using the error detecting code, and in response to detecting the error, to regenerate the error detecting code using the redundant information, and to determine whether a resulting regenerated error detecting code is correct using the error detecting code.

3. The system as recited in claim 2, wherein the receiver is further configured to regenerate a different bit of the segment of data using the redundant information in response to determining that the resulting regenerated bit, along with remaining bits, of the segment of data are not correct.

4. The system as recited in claim 1, wherein the error detecting code is an error correcting code.

5. The system as recited in claim 1, wherein the redundant information is conveyed from the transmitter to the receiver serially via a single bit lane and includes parity information corresponding to bits of the segment of data and the error detecting code conveyed in a given clock cycle.

6. The system as recited in claim 1, wherein in response to determining that the resulting regenerated bit, along with remaining bits, of the segment of data are correct, the receiver is further configured to regenerate bits of the segment of data conveyed on a same bit lane using the redundant information when receiving subsequent transmissions.

7. The system as recited in claim 1, wherein in response to detecting the error, the receiver is configured to request the transmitter resend the segment of data, the error detecting code, and the redundant information a predetermined number of times prior to regenerating the segment of data using the redundant information.

8. A method comprising:

transmitting a segment of data, a cyclic redundancy code, and redundant information; and

conveying the segment of data, the cyclic redundancy code, and the redundant information via separate bit lanes of a communication link including a plurality of bit lanes, wherein each bit of the segment of data, and the cyclic redundancy code is conveyed from the transmitter to the receiver serially via a respective single-bit lane;

accumulating the segment of data, the redundant information, and the cyclic redundancy code within the receiver over a plurality of clock cycles;

wherein the cyclic redundancy code covers the segment of data accumulated over the plurality of clock cycles, and wherein the cyclic redundancy code is defined by a serial sequence of the bits of the segment of data conveyed upon each bit lane concatenated with the bits of the segment of data conveyed upon a next bit lane;

detecting an error in the segment of data using the cyclic redundancy code, and in response to detecting the error, regenerating the segment of data using the redundant information; and

determining whether a resulting regenerated bit, along with remaining bits, of the segment of data is correct using the cyclic redundancy code.

9. The method as recited in claim 8, further comprising detecting an error in the error detecting code using the error detecting code, and in response to detecting the error, regenerating the error detecting code using the redundant information, and determining whether a resulting regenerated error detecting code is correct using the error detecting code.

10. The method as recited in claim 9, further comprising regenerating a different bit of the segment of data using the redundant information in response to determining that the resulting regenerated bit, along with remaining bits, of the segment of data are not correct.

11. The method as recited in claim 8, wherein the error detecting code is an error correcting code.

12. The method as recited in claim 8, wherein the redundant information includes parity information corresponding to bits of the segment of data and the error detecting code conveyed in a given clock cycle.

13. The method as recited in claim 8, in response to determining that the resulting regenerated bit, along with remaining bits, of the segment of data are correct, regenerating bits of the segment of data conveyed on a same bit lane using the redundant information when receiving subsequent transmissions.

14. The method as recited in claim 8, further comprising in response to detecting the error, requesting the transmitter resend the segment of data, the error detecting code, and the redundant information a predetermined number of times prior to regenerating the segment of data using the redundant information.

15. A system comprising:

means for transmitting a segment of data, a cyclic redundancy code, and redundant information; and

means for conveying the segment of data, the cyclic redundancy code, and the redundant information via separate bit lanes of a communication link including a plurality of bit lanes, wherein each bit of the segment of data, and the cyclic redundancy code is conveyed from the transmitter to the receiver serially via a respective single-bit lane;

means for accumulating the segment of data, the redundant information, and the cyclic redundancy code within the receiver over a plurality of clock cycles, wherein the cyclic redundancy code covers the segment of data accumulated over the plurality of clock cycles, and wherein the cyclic redundancy code is defined by a serial sequence of the bits of the segment of data conveyed upon each bit lane concatenated with the bits of the segment of data conveyed upon a next bit lane;

means for detecting an error in the segment of data using the cyclic redundancy code, and in response to detecting the error, regenerating the segment of data using the redundant information; and

means for determining whether a resulting regenerated bit, along with remaining bits, of the segment of data is correct using the cyclic redundancy code.

16. A system comprising:

a transmitter configured to transmit, via separate bit lanes of a communication link including a plurality of bit lanes, a segment of data, a cyclic redundancy code, and redundant information;

wherein the cyclic redundancy code covers the segment of data accumulated over the plurality of clock cycles, and wherein the cyclic redundancy code is defined by a serial sequence of the bits of the segment of data conveyed upon each bit lane concatenated with the bits of the segment of data conveyed upon a next bit lane; and

a receiver coupled to the transmitter via the communication link, wherein the receiver is configured to detect an error in the segment of data using the cyclic redundancy code, and in response to detecting the error, for each bit of the segment of data, to iteratively regenerate at least one bit of the segment of data using the redundant information;

wherein the receiver is further configured to determine whether the resulting regenerated bit, along with the remaining bits, of the segment of data are correct using the cyclic redundancy code.