Electrically isolated pillars in active devices

• US 7,413,945 B2
• Filed: 10/07/2003
• Issued: 08/19/2008
• Est. Priority Date: 06/27/2002
• Status: Expired due to Fees

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: SanDisk 3D LLC (Western Digital Corporation)
• Inventors: Cleeves, James M., Bhatia, Manish, Knall, N. Johan, Vyvoda, Michael A.
• Primary Examiner(s): MENZ, LAURA MARY
• Application Number:
  US10/681,507
• Publication Number:
  US 20040071034A1
• Time in Patent Office: 1,778 Days
• Field of Search: 438/200, 438/197, 438/237
• US Class Current: 438/200
• CPC Class Codes: H10B 99/16 comprising memory cells having diodes

Abstract

A method of forming an active device is provided. The method includes performing a first patterning operation on a first plurality of layers. This first patterning operation defines a first feature of the active device. Then, a second patterning operation can be performed on at least one layer of the first plurality of layers. This second patterning operation defines a second feature of the active device. Of importance, the first and second patterning operations are performed substantially back-to-back, thereby ensuring that the active device can accurately function.

Claims

1. A method of forming an active device, the method comprising:

performing a first patterning operation having a first pattern on a first plurality of layers comprising etching the first plurality of layers into a first plurality of strips oriented in a first direction, the first patterning operation defining a first feature of the active device; and

performing a second patterning operation having a second pattern comprising etching at least one strip of the first plurality of strips in a second direction, the second direction being different than the first direction to create a pillar on at least one patterned layer of the first plurality of layers, the second patterning operation defining a second feature of the active device, wherein the first and second patterning operations are performed substantially back-to-back.

2. The method of claim 1, wherein the

first plurality of layers includes at least one of a P-type layer and an N-type layer.

3. The method of claim 2, wherein a three-dimensional array of diodes is formed.

4. The method of claim 1, wherein at least one strip of the first plurality of strips comprises a first terminal of the active device.

5. The method of claim 4, wherein the pillar comprises another portion of the active device.

6. The method of claim 4, further including:

depositing a first dielectric after both first and second patterning operations; and

planarizing the first dielectric to expose a surface of the active device.

7. The method of claim 6, further including performing a cleaning step after planarizing.

8. The method of claim 6, further including:

depositing a second plurality of layers on the surface of the active device and the first dielectric; and

etching the second plurality of layers into a second plurality of strips oriented in the second direction.

9. The method of claim 8, wherein said second plurality of strips is not self-aligned in the pillar.

10. The method of claim 8, wherein at least one strip of the second plurality of strips comprises a second terminal of the active device.

11. The method of claim 1, wherein the first plurality of layers include an antifuse layer fully etched though by the first patterning operation, but not fully etched though by the second patterning operation.

12. The method of claim 1, wherein the first plurality of layers includes an antifuse layer fully etched though by both the first and second patterning operations.

13. The method of claim 1, wherein the first plurality of strips include first terminals of an array of diodes.

14. The method of claim 1, wherein unetched strips of the first plurality of strips comprise a portion of an array of diodes and etched strips of the first plurality of strips comprise another portion of the diodes.

15. The method of claim 13, further including:

depositing a first dielectric after first and second patterning operations; and

planarizing the first dielectric to expose a surface of the diodes.

16. The method of claim 15, further including performing a cleaning step following planarization.

17. The method of claim 13, wherein the first plurality of layers includes an antifuse layer fully etched through by the first and second patterning operations.

18. The method of claim 13, wherein the array is a three-dimensional array and a portion of the second plurality of strips is etched in the first direction to form another plane of diodes.

19. A method of forming an active device of claim 1, further comprising:

the first patterning operation defining a first terminal of the active device;

the second patterning operation defining a first feature of the active device; and

performing a third patterning operation on a second plurality of layers, wherein the third patterning operation defines a second feature and a second terminal of the active device.

20. The method of claim 19, further including:

depositing a first dielectric after both first and second patterning operations; and

planarizing the first dielectric to expose a surface of the active device.

21. The method of claim 20, wherein performing the third patterning operation is preceded by steps including:

depositing a second plurality of layers on the surface of the active device and the first dielectric; and

etching the second plurality of layers into a second plurality of strips oriented in the second direction.

22. The method of claim 21, wherein at least one strip of the second plurality of strips comprises the second feature, and wherein at least one other strip of second plurality of strips comprises the second terminal of the active device.

23. The method of claim 6, further including growing antifuse material on the exposed surface of the active device.

24. The method of forming

an active device of claim 1, the first plurality of layers including a first silicon-type layer;

and

the second patterning operation defining one feature of a plurality of diodes from the first silicon-type layer.

25. The method of claim 24, wherein the first plurality of strips include first terminals of the diodes.

26. The method of claim 25, further including:

depositing a first dielectric after first and second patterning operations; and

planarizing the first dielectric to expose a surface of the diodes.

27. The method of claim 26, further including performing to HF dip following planarizing.

28. The method of claim 25, wherein the second plurality of strips include second features and second terminals of the diodes.

29. The method of claim 26, further including growing antifuse material on the exposed surfaces of the diodes.

30. The method of claim 29, wherein the diodes form a three-dimensional array and a portion of the second plurality of strips are etched in the first direction to form features of another plane of diodes.

31. The method of forming an active device of claim 1 wherein the first patterning operation comprises

a first anisotropic etch the first plurality of layers, and

the second patterning operation comprises a second anisotropic etch.

32. The method of claim 31, wherein the first plurality of layers includes at least one silicon-type layer.

33. The method of claim 31, wherein the first plurality of layers includes at least one refractory metal layer.

34. The method of claim 31, wherein the first plurality of layers includes an antifuse layer.

35. The method of forming

an active device of claim 1 wherein the first plurality of layers includes an N layer and two P+ layers sandwiching an antifuse layer;

and

the second patterning operation is performed on at least the N layer of the first plurality of strips.

36. The method of claim 35, wherein the first plurality of strips include terminals of an array of diodes.

37. The method of claim 36, wherein unetched strips of the first plurality of strips comprise first terminals of the diodes and etched strips of the first plurality of strips comprise at least a portion of the diodes.

38. The method of claim 37, further including:

depositing a first dielectric after first and second patterning operations; and

planarizing the first dielectric to expose a surface of the diodes.

39. The method of claim 38, further including performing a cleaning step following planarization.

40. The method of claim 35, wherein the first plurality of layers includes the antifuse layer fully etched through by the first and second patterning operations.

41. The method of claim 37, wherein the array is a three-dimensional array and a portion of the second plurality of strips are etched in the first direction to form another plane of diodes.