Insulated gate semiconductor device and manufacturing method of the same

• US 7,413,954 B2
• Filed: 09/21/2005
• Issued: 08/19/2008
• Est. Priority Date: 09/27/2004
• Status: Active Grant

• Current Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Original Assignee: Sanyo Electric Company Limited (Panasonic Holdings Corporation)
• Inventors: Saito, Hiroaki, Yanagida, Masamichi, Iwata, Satoshi, Onda, Masahito, Kubo, Hirotoshi, Tojo, Junichiro
• Primary Examiner(s): CHAUDHARI, CHANDRA P
• Application Number:
  US11/230,538
• Publication Number:
  US 20060065926A1
• Time in Patent Office: 1,063 Days
• Field of Search: 438/206, 438/212, 438/270, 438/272, 438/589, 257/E21.419, 257/E21.629
• US Class Current: 438/270
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

A capacity layer is formed of non-doped polysilicon. Unlike capacity layers formed of an oxide film, generation of seams and the like can be suppressed and thereby a stable capacity layer can be formed. Moreover, polysilicon used as a capacity layer may be doped polysilicon, and an oxide film formed on the surface of the polysilicon also serves as a capacity film. Thus, provision of an insulated gate device featuring low capacity is made possible.

Claims

1. A method of manufacturing an insulated gate semiconductor device, comprising:

forming on a semiconductor layer of a first general conduction type a channel layer of a second general conduction type;

forming a trench which penetrates the channel layer and reaches the semiconductor layer so that the trench comprises a channel layer trench portion that is formed in the channel layer and a semiconductor layer trench portion that is formed in the semiconductor layer;

forming a first insulating film on an inner wall of the trench;

forming a first semiconductor layer at the semiconductor layer trench portion of the trench;

forming a second insulating film on the inner wall of the trench so that the second insulating film is formed on the first insulating film disposed at the channel layer trench portion of the trench and on the first semiconductor layer;

forming in the trench a second semiconductor layer that is disposed on the first semiconductor layer; and

forming a source region of the first general conduction type in a surface of the channel layer and adjacent the trench.

2. The method of claim 1, wherein the forming of the first semiconductor layer comprises a deposition of a non-doped polysilicon.

3. The method of claim 1, wherein the forming of the first semiconductor layer is performed between the forming of the first insulating film and the forming of the second insulating film.