High voltage silicon carbide MOS-bipolar devices having bi-directional blocking capabilities

• US 7,414,268 B2
• Filed: 05/18/2005
• Issued: 08/19/2008
• Est. Priority Date: 05/18/2005
• Status: Active Grant

• Current Assignee: CREE Incorporated (Wolfspeed, Inc.)
• Original Assignee: CREE Incorporated (Wolfspeed, Inc.)
• Inventors: Agarwal, Anant K., Hobgood, Hudson McDonald, Ryu, Sei-Hyung, Das, Mrinal K., Palmour, John W., Jenny, Jason R.
• Primary Examiner(s): Hu; Shouxiang
• Application Number:
  US11/132,355
• Publication Number:
  US 20060261347A1
• Time in Patent Office: 1,189 Days
• Field of Search: 257/77, 257/329, 257/339
• US Class Current: 257/77
• CPC Class Codes: H01L 29/1608 Silicon carbide
• CPC Class Codes: H01L 29/66068 the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
• CPC Class Codes: H01L 29/66333 Vertical insulated gate bipolar transistors
• CPC Class Codes: H01L 29/7395 Vertical transistors, e.g. vertical IGBT

Abstract

Silicon carbide high voltage semiconductor devices and methods of fabricating such devices are provided. The devices include a voltage blocking substrate. Insulated gate bipolar transistors are provided that have a voltage blocking substrate. Planar and beveled edge termination may be provided.

Claims

1. A high voltage silicon carbide (SiC) device, comprising:

a SiC insulated gate bipolar transistor (IGBT) comprising a voltage blocking substrate as a drift region of the IGBT;

a planar edge termination structure at a first surface of the voltage blocking substrate and surrounding an active region of the IGBT;

a beveled edge termination structure extending through a second surface of the voltage blocking substrate opposite the first surface of the voltage blocking substrate, wherein the voltage blocking substrate is a boule grown substrate; and

an epitaxial silicon carbide layer formed on the second surface of the voltage blocking substrate,

wherein the planar edge termination structure includes a plurality of floating guard rings;

wherein the epitaxial silicon carbide layer has a conductivity type opposite to a conductivity type of the voltage blocking substrate; and

wherein the voltage blocking substrate includes an upper portion having a substantially vertical edge and a lower portion having a beveled edge extending to a bottom surface of the epitaxial silicon carbide layer, so as to form the beveled edge termination structure.

2. The device of claim 1, wherein the voltage blocking substrate comprises a 4H—

SiC high purity substrate having a carrier concentration no greater than about 1.0×

10¹⁵ cm<sup>−

3</sup>.

3. The device of claim 2, wherein the voltage blocking substrate has a thickness of greater than about 100 μ

m.

4. The device of claim 1, wherein the voltage blocking substrate comprises an n-type SiC substrate.

5. The device of claim 1, wherein the voltage blocking substrate comprises a p-type SiC substrate.

6. A high voltage silicon carbide (SiC) device, comprising:

a first SiC layer having a first conductivity type on a first surface of a voltage blocking SiC substrate having a second conductivity type opposite to the first conductivity type;

a first region of SiC at a second surface of the voltage blocking substrate and having the first conductivity type;

a second region of SiC in the first region of SiC, the second region having the first conductivity type and having a carrier concentration higher than a carrier concentration of the first region;

a third region of SiC in the first region of SiC, the third region having the second conductivity type;

an insulator layer on the second surface of the voltage blocking substrate;

a gate electrode on the insulator layer and adjacent the first and third regions of SiC;

a first contact on the second and third regions of SiC;

a second contact on a bottom surface of the first SiC layer, wherein the voltage blocking substrate is a boule grown substrate;

a planar edge termination structure at the second surface of the voltage blocking substrate; and

a beveled edge termination structure at the first surface of the voltage blocking substrate opposite to the second surface of the substrate,

wherein the planar edge termination structure includes a plurality of floating guard rings; and

wherein the voltage blocking substrate includes an upper portion having a substantially vertical edge and a lower portion having a beveled edge extending to the bottom surface of the first SiC layer, so as to form the beveled edge termination structure.

7. The device of claim 6, wherein the voltage blocking substrate comprises a 4H—

SiC high purity substrate having a carrier concentration no greater than about 1.0×

10¹⁵ cm<sup>−

3</sup>.

8. The device of claim 7, wherein the voltage blocking substrate has a thickness of greater than about 100 μ

m.

9. The device of claim 6, wherein the first conductivity type comprises p-type SiC and the second conductivity type comprises n-type SiC.

10. The device of claim 6, wherein the first conductivity type comprises n-type SiC and the second conductivity type comprises p-type SiC.

11. The device of claim 6, wherein the first SiC layer has a thickness of from about 0.1 to about 20.0 μ

m.

12. The device of claim 6, wherein the first SiC layer has a carrier concentration of from about 1×

10¹⁶ to about 1×

10²¹ cm<sup>−

3</sup>.

13. The device of claim 6, wherein the first SiC region has a carrier concentration of from about 1×

10¹⁵ to about 5×

10^·

cm<sup>−

3</sup>.

14. The device of claim 6, wherein the first SiC region has a depth of from about 0.3 to about 2.0 μ

m.

15. The device of claim 6, wherein the second SiC region has a carrier concentration of from about 5×

10¹⁷ to about 1×

10²¹ cm<sup>−

3</sup>.

16. The device of claim 6, wherein the second SiC region has a depth of from about 0.1 to about 2.0 μ

m.

17. The device of claim 6, wherein the third SiC region has a carrier concentration of from about 5×

10¹⁷ to about 1×

10²¹ cm<sup>−

3</sup>.

18. The device of claim 6, wherein the third SiC region has a depth of from about 0.1 to about 1.5 μ

m.

19. The device of claim 6, wherein the floating guard rings have a carrier concentration of from about 5×

10¹⁷ to about 1×

10²¹ cm<sup>−

3</sup>.

20. The device of claim 6, wherein the floating guard rings have a depth of from about 0.1 to about 2.0 μ

m.

21. The device of claim 6, wherein the floating guard rings have the second conductivity types;

wherein the first SiC layer has a thickness of from about 0.1 to about 20.0 μ

m and a carrier concentration of from about 1×

10¹⁶ to about 1×

10²¹ cm<sup>−

3</sup>;

wherein the first SiC region has a carrier concentration of from about 1×

10¹⁵ to about 5×

10¹⁹ cm<sup>−

3</sup> and a depth of from about 0.3 to about 2.0 μ

m;

wherein the second SiC region has a carrier concentration of from about 5×

10¹⁷ to about 1×

10²¹ cm<sup>−

3</sup> and a depth of from about 0.1 to about 2.0 μ

m;

wherein the third SiC region has a carrier concentration of from about 5×

10¹⁷ to about 1×

10²¹ cm<sup>−

3</sup> and a depth of from about 0.1 to about 1.5 μ

m; and

wherein the the floating guard rings have a carrier concentration of from about 5×

10¹⁷ to about 1×

10²¹ cm<sup>−

3</sup> and a depth of from about 0.1 to about 2.0 μ

m.