Waferscale package system

• US 7,414,310 B2
• Filed: 02/02/2006
• Issued: 08/19/2008
• Est. Priority Date: 02/02/2006
• Status: Active Grant

• Current Assignee: JCET Semiconductor (Shaoxing) Co., Ltd.
• Original Assignee: Stats Chippac BVI limited (JCET Group Co., Ltd.)
• Inventors: Do, Byung Tai, Yang, Sung Uk
• Primary Examiner(s): CLARK, SHEILA V
• Application Number:
  US11/307,363
• Publication Number:
  US 20070176280A1
• Time in Patent Office: 929 Days
• Field of Search: 257/81, 257/99, 257/100, 257/432, 257/433, 257/704, 257/710, 257/173, 257/E23.002
• US Class Current: 257/710
• CPC Class Codes: B81C 1/00333 Aspects relating to packaging of MEMS devices, not covered by groups B81C1/00269 - B81C1/00325
• CPC Class Codes: B81C 2203/0109 Bonding an individual cap on the substrate
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/32245 the item being metallic
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/48247 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/73265 Layer and wire connectors
• CPC Class Codes: H01L 24/73 Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/10253 Silicon [Si]
• CPC Class Codes: H01L 2924/14 Integrated circuits
• CPC Class Codes: H01L 2924/15311 being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/3025 Electromagnetic shielding
• CPC Class Codes: H01L 31/0203 Containers; Encapsulations , e.g. encapsulation of photodiodesfor photovoltaic devices H01L31/048; for organic photosensitive devices H10K30/80

Abstract

A waferscale package system is provided forming a protection structure comprises forming a wafer, fabricating a device element on the wafer, forming a waferscale spacer around the device element, and attaching a waferscale cap to the waferscale spacer to cover the device element, attaching a carrier to the protection structure, and molding an encapsulant around the protection structure to the carrier.

Claims

1. A waferscale package system comprising:

forming a protection structure comprises;

forming a wafer,

fabricating a device element on the wafer,

forming a waferscale spacer around the device element and having a thickness greater than a width thereof and greater than the thickness of the device element, and

attaching a waferscale cap to the waferscale spacer to cover the device element;

attaching a carrier to the protection structure;

electrically connecting the wafer outside the waferscale spacer to the carrier with bond wires; and

molding an encapsulant around the protection structure to the carrier.

2. The system as claimed in claim 1 wherein fabricating the device element on the wafer comprises fabricating a microelectromechanical system element.

3. The system as claimed in claim 1 wherein fabricating the device element on the wafer comprises fabricating an optical element with the waferscale cap optically transparent.

4. The system as claimed in claim 1 wherein forming the waferscale spacer around the device element comprises forming a dam type waferscale spacer with the waferscale cap for preventing the encapsulant from interfering with the device element.

5. The system as claimed in claim 1 wherein forming the waferscale spacer around the device element comprises forming a step-dam type waferscale spacer with the waferscale cap, on a step of the step-dam waferscale spacer, for preventing the encapsulant from interfering with the device element.

6. A waferscale package system comprising:

forming a protection structure comprises;

forming a wafer,

fabricating a device element on the wafer,

forming a waferscale spacer around the device element and having a thickness greater than width thereof and greater than the thickness of the device element,

attaching a waferscale cap to the waferscale spacer to cover the device element, and singulating the wafer to form a number of a semiconductor die;

attaching a carrier to the protection structure;

electrically connecting the semiconductor die outside the waferscale spacer to the carrier with bond wires; and

molding an encapsulant around the protection structure to the carrier.

7. The system as claimed in claim 6 wherein molding the encapsulant around the protection structure to the carrier comprises exposing a top of the waferscale cap.

8. The system as claimed in claim 6 wherein molding the encapsulant around the protection structure to the carrier comprises forming a hermetic seal of the protection structure.

9. The system as claimed in claim 6 wherein forming the wafer comprises forming an optical structure.

10. The system as claimed in claim 6 further comprising attaching electrical interconnects between carrier and bonding pads of the semiconductor die.

11. A waferscale package system comprising:

a protection structure comprises;

a semiconductor die,

a device element on the semiconductor die,

a waferscale spacer around the device element and having a thickness greater than a width thereof and greater than the thickness of the device element, and

a waferscale cap attached to the waferscale spacer to cover the device element;

a carrier attached to the protection structure;

bond wires electrically connecting the wafer outside the waferscale spacer to the carrier; and

an encapsulant around the protection structure to the carrier.

12. The system as claimed in claim 11 wherein the device element on the semiconductor die is a microelectromechanical system element.

13. The system as claimed in claim 11 wherein the device element on the semiconductor die is an optical element with the waferscale cap optically transparent.

14. The system as claimed in claim 11 wherein the waferscale spacer around the device element is a dam type waferscale spacer with the waferscale cap for preventing the encapsulant from interfering with the device element.

15. The system as claimed in claim 11 wherein the waferscale spacer around the device element is a step-dam type waferscale spacer with the waferscale cap, on a step of the step-dam waferscale spacer, for preventing the encapsulant from interfering with the device element.

16. The system as claimed in claim 11 wherein the carrier is a substrate or lead frame.

17. The system as claimed in claim 16 wherein the encapsulant around the protection structure to the carrier comprises a top of the waferscale cap exposed.

18. The system as claimed in claim 16 wherein the encapsulant around the protection structure to the carrier forms a hermetic seal by the encapsulant of the protection structure.

19. The system as claimed in claim 16 wherein the semiconductor die supports an optical structure.

20. The system as claimed in claim 16 further comprising electrical interconnects between carrier and bonding pads of the semiconductor die.