Circuits, systems and methods relating to dynamic ring oscillators
First Claim
1. A dynamic oscillating ring circuit, comprising:
- a plurality of domino circuits, each comprising a signal input, a trigger input, an input relating to a charge state clock, an input relating to a clocked cutoff, and an output inverter; and
a plurality of non-inverting stages, each comprising a number of said domino circuits coupled in a chain wherein the first domino circuit of said chain receives a logic signal input and a single trigger input for said chain, wherein an output of each said domino circuit comprises an input to said signal input of a next domino circuit in said chain, wherein said plurality of said stages is configured as a non-inverting ring wherein an output of each stage comprises an input signal to a next stage and is fed back to clock an earlier stage to allow oscillation in said ring.
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Abstract
A dynamic oscillating ring circuit is described, which has multiple non-inverting domino circuits, each having a signal input, a trigger input, inputs for charge state clock and clocked cutoff and an output inverter. A number of the domino circuits are coupled in series, the output of one feeding the input of the next, to form a chain, which form stages of the ring. A number of the stages are coupled in series, the output of one feeding the input of the next, to form the ring. The first domino circuit of said chain receives a logic signal input and a single trigger input for the chain. Within the ring, the output of each stage feeds the input signal to the next stage and is fed back to clock an earlier stage to allow the ring to oscillate.
110 Citations
66 Claims
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1. A dynamic oscillating ring circuit, comprising:
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a plurality of domino circuits, each comprising a signal input, a trigger input, an input relating to a charge state clock, an input relating to a clocked cutoff, and an output inverter; and a plurality of non-inverting stages, each comprising a number of said domino circuits coupled in a chain wherein the first domino circuit of said chain receives a logic signal input and a single trigger input for said chain, wherein an output of each said domino circuit comprises an input to said signal input of a next domino circuit in said chain, wherein said plurality of said stages is configured as a non-inverting ring wherein an output of each stage comprises an input signal to a next stage and is fed back to clock an earlier stage to allow oscillation in said ring. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15)
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16. A system for determining the relative strength of N-type and P-type devices of a circuit, said system comprising:
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an oscillator having N-type components and P-type components and generating an output, the frequency of which comprises characteristics generated by said N-type components and said P-type components; a detector coupled to said output for detecting said N-type and said P-type characteristic frequencies and generating a signal corresponding to said detecting; a comparator coupled to said detector for comparing said N-type and said P-type characteristics based on said detector signals and generating a corresponding comparison signal; and a determinator coupled to said comparator for determining said relative strength of said N-type and said P-type devices based on said comparison. - View Dependent Claims (17, 18, 19)
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20. A method for determining relative strength of N-type and P-type devices of a circuit, said method comprising:
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resolving a frequency of operation of said circuit into components respectively contributed by said N-type and said P-type components; comparing said N-type components and said P-type components; and based on said comparing, determining said relative strength of N-type and P-type devices. - View Dependent Claims (21, 22)
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23. An N-domino ring oscillator circuit, comprising:
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a plurality of non-inverting N-footed domino circuits, each N-footed domino circuit having a signal input, a trigger input, a precharge clock input, a clocked cutoff input, and an output inverter; a plurality of non-inverting stages, each stage comprising a chain of a number of said N-domino circuits coupled in series wherein the first N-domino circuit of said chain receives a logic signal input and a single trigger input for said chain, wherein an output of each said N-domino circuit comprises the input to said signal input of the next N-domino circuit in said chain; and a non-inverting N-domino ring, comprising a plurality of said stages wherein an output of each stage comprises an input signal to the next stage and is fed back to clock an earlier stage to allow oscillation in said ring, wherein said N-domino circuits comprising said stages evaluate on the basis of said input, wherein, upon said oscillation traversing said ring to the last stage thereof, the precharge state of said first stage has reset wherein said first stage is ready to evaluate upon the output of said last stage, said output of said last stage resulting from said last stage evaluating on the basis of said oscillation. - View Dependent Claims (24, 25, 26, 27, 28, 29, 30)
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31. A self-untriggered N-domino ring component in an oscillating circuit, said self-untriggered N-domino ring component comprising:
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a plurality of non-inverting N-footed domino circuits, each N-footed domino circuit having a signal input, a trigger input, a precharge clock input, a clocked cutoff input, and an output inverter; a plurality of non-inverting stages, each stage comprising a chain of a number of said N-domino circuits coupled in series wherein the first N-domino circuit of said chain receives a logic signal input and a single trigger input for said chain, wherein an output of each said N-domino circuit comprises the input to said signal input of the next N-domino circuit in said chain; and a non-inverting and self-untriggered N-domino ring, comprising a plurality of said stages wherein an output of each stage comprises an input signal to the next stage and is fed back to clock an earlier stage to allow oscillation in said ring, wherein said N-domino circuits comprising said stages evaluate on the basis of said input. - View Dependent Claims (32, 33, 34, 35, 36, 37, 38, 39)
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40. A P-domino ring oscillator circuit, comprising:
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a plurality of non-inverting P-footed domino circuits, each P-footed domino circuit having a signal input, a trigger input, a pre-discharge clock input, a clocked cutoff input, and an output inverter; a plurality of non-inverting stages, each stage comprising a chain of a number of said P-domino circuits coupled in series wherein the first P-domino circuit of said chain receives a logic signal input and a single trigger input for said chain, wherein an output of each said P-domino circuit comprises the input to said signal input of the next P-domino circuit in said chain; and a non-inverting P-domino ring, comprising a plurality of said stages wherein an output of each stage comprises an input signal to the next stage and is fed back to clock an earlier stage to allow oscillation in said ring. - View Dependent Claims (41, 42, 43, 44, 45, 46, 47, 48, 49, 50)
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51. A dynamic ring circuit for oscillating at a low voltage, said dynamic ring circuit comprising:
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a plurality of un-latched non-inverting domino circuits, each non-inverting domino circuit having a signal input, a trigger input, an input relating to a charge state clock, an input relating to a clocked cutoff, and an output inverter; a plurality of non-inverting stages, each stage comprising of a number of said unlatched domino circuits coupled in series wherein the first unlatched domino circuit of said chain receives a logic signal input and a single trigger input for said chain, wherein an output of each said unlatched domino circuit comprises the input to said signal input of the next unlatched domino circuit in said chain; and a non-inverting ring, comprising a plurality of said stages wherein an output of each stage comprises an input signal to the next stage and is fed back to clock an earlier stage to allow oscillation in said ring wherein said ring oscillates at said low voltage. - View Dependent Claims (52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62)
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63. A half latch jamb component for a domino circuit, said half latch jamb component comprising:
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a first transistor coupled to a supply voltage for said domino circuit; a second transistor coupled in series to said first transistor; and a third transistor coupled in series to said second transistor and to an input of an inverter, wherein said inverter comprises an output stage of said domino circuit and wherein said first, second and third transistors are gated together in parallel by an output of said inverter. - View Dependent Claims (64, 65, 66)
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Specification