Enhanced-accuracy converter stages for pipelined signal converter systems

• US 7,414,564 B1
• Filed: 06/18/2007
• Issued: 08/19/2008
• Est. Priority Date: 06/18/2007
• Status: Active Grant

• Current Assignee: Analog Devices, Inc.
• Original Assignee: Analog Devices, Inc.
• Inventors: Ali, Ahmed Mohamed Abdelatty
• Primary Examiner(s): Nguyen; Khai M
• Application Number:
  US11/820,298
• Time in Patent Office: 428 Days
• Field of Search: 341/118, 341/161, 341/162, 341/172
• US Class Current: 341/161
• CPC Class Codes: H03M 1/0607 Offset or drift compensation removal of offset already present on the analogue input signal H03M1/1295
• CPC Class Codes: H03M 1/0695 using less than the maximum number of output states per stage or step, e.g. 1.5 per stage or less than 1.5 bit per stage type
• CPC Class Codes: H03M 1/44 Sequential comparisons in series-connected stages with change in value of analogue signal

Abstract

Converter systems are provided which complement sample capacitors in at least one converter stage with replica capacitors. The replica capacitors are switched to receive replica charges from the analog input signal during the same operational mode in which the sample capacitors receive undesirable remnant charges. In an initial portion of a subsequent operational mode, the remnant capacitors are briefly switched to the sample capacitors to substantially cancel the remnant charges. The sample capacitors then participate in obtaining input-signal samples during the remainder of the subsequent operational mode. Because the remnant charges have been substantially canceled, the accuracy of the subsequent operational mode is considerably enhanced. In another system embodiment, the replica capacitor is replaced by a discharge switch which provides a discharge path in an initial portion of the subsequent operational mode.

Claims

1. A converter stage configured to process an analog input signal to a corresponding digital code and a residue signal in sample and gain operational modes, comprising:

a switched-capacitor residue generator having at least one sample capacitor and an amplifier and arranged to switchably direct, in said sample mode, a sample of said input signal to said sample capacitor and to switchably couple, in said gain mode, said sample capacitor between a selected one of a plurality of reference signals and said amplifier to thereby provide said residue signal with a remnant charge thereby remaining in said sample capacitor;

a flash converter arranged to receive said sample during said sample mode and to provide said corresponding digital code and identify said selected reference signal during said gain mode; and

at least one replica capacitor arranged to switchably receive a replica charge in said gain mode and to be switchably coupled to said sample capacitor in a portion of said sample mode to thereby substantially cancel said remnant charge with said replica charge.

2. The stage of claim 1, wherein said generator includes a reference switch which couples said sample capacitor to said selected reference signal in said gain mode and further including at least one replica switch that couples a first plate of said replica capacitor to a different one of said reference signals in said gain mode and couples said first plate to said sample capacitor in said portion.

3. The stage of claim 1, wherein said different reference signal is a dummy reference signal.

4. The stage of claim 1, wherein said generator includes a reference switch which couples said sample capacitor to said selected reference signal in said gain mode and further including at least one replica switch that couples a first plate of said replica capacitor to said selected reference signal in said gain mode and couples a second plate of said replica capacitor to said sample capacitor in said portion.

5. The stage of claim 1, wherein said generator includes a reference switch which couples said sample capacitor to said selected reference signal in said gain mode and further including at least one replica switch that couples a first plate of said replica capacitor to a dummy version of said selected reference signal in said gain mode and couples a second plate of said replica capacitor to said sample capacitor in said portion.

6. The stage of claim 1, wherein said generator includes an output capacitor coupled about said amplifier.

7. The stage of claim 1, wherein said generator includes an upstream sample switch arranged to provide said sample in said sample mode.

8. The stage of claim 7, wherein said sample switch is a transistor.

9. The stage of claim 7, wherein said generator further includes an upstream emitter follower inserted to pass said input signal to said sample switch.

10. The stage of claim 1, wherein said sample and replica capacitors are equally sized.

11. The stage of claim 1, wherein said generator includes:

a first sample switch that provides a signal path to a first plate of said sample capacitor in said sample mode; and

a second sample switch that extends said signal path from a second plate of said sample capacitor in at least a portion of said sample mode.

12. A converter stage configured to process an analog input signal to a corresponding digital code and a residue signal in sample and gain operational modes, comprising:

a switched-capacitor residue generator having at least one sample capacitor and an amplifier and arranged to switchably direct, in said sample mode, a sample of said input signal to said sample capacitor and to switchably couple, in said gain mode, said sample capacitor between a selected one of a plurality of reference signals and said amplifier to thereby provide said residue signal with a remnant charge thereby remaining in said sample capacitor;

a flash converter arranged to receive said sample during said sample mode and to provide said corresponding digital code and identify said selected reference signal during said gain mode; and

a discharge switch coupled to said sample capacitor to provide a discharge path that substantially discharges said remnant charge in a portion of said sample mode.

13. The stage of claim 12, wherein said generator includes a sample switch arranged to provide said sample in said sample mode.

14. The stage of claim 13, wherein said sample switch is a transistor.

15. The stage of claim 13, wherein said generator further includes an upstream emitter follower inserted to pass said input signal to said sample switch.

16. The stage of claim 12, wherein said generator includes:

a first sample switch that provides a signal path to a first plate of said sample capacitor in said sample mode; and

a second sample switch that extends said signal path from a second plate of said sample capacitor in at least a portion of said sample mode.

17. A signal converter system for converting an analog input signal into a corresponding digital code, the system comprising:

N converter stages that successively convert said input signal to corresponding digital bits wherein all but an Nth one of said stages provides a residue signal for processing by a succeeding one of said stages; and

an aligner/corrector that provides said corresponding digital code in response to said digital bits;

wherein at least one of said stages processes said input signal to corresponding digital bits and a residue signal in sample and gain operational modes and includes;

a switched-capacitor residue generator having at least one sample capacitor and an amplifier and arranged to switchably direct, in said sample mode, a sample of said input signal to said sample capacitor and to switchably couple, in said gain mode, said sample capacitor between a selected one of a plurality of reference signals and said amplifier to provide said residue signal and thereby insert a remnant charge in said sample capacitor;

a flash converter arranged to receive said sample during said sample mode and to provide said corresponding digital code and identify said selected reference signal during said gain mode; and

at least one replica capacitor arranged to switchably receive a replica charge in said gain mode and to be switchably coupled to said replica capacitor in a first portion of said sample mode to thereby substantially eliminate said remnant charge with said replica charge.

18. The system of claim 17, wherein said generator includes a reference switch which couples said sample capacitor to said selected reference signal in said gain mode and further including at least one replica switch that couples a first plate of said replica capacitor to a different one of said reference signals in said gain mode and couples said first plate to said sample capacitor in said portion.

19. The system of claim 17, wherein said generator includes a reference switch which couples said sample capacitor to said selected reference signal in said gain mode and further including at least one replica switch that couples a first plate of said replica capacitor to said selected reference signal in said gain mode and couples a second plate of said replica capacitor to said sample capacitor in said portion.

20. The system of claim 17, wherein said generator includes a reference switch which couples said sample capacitor to said selected reference signal in said gain mode and further including at least one replica switch that couples a first plate of said replica capacitor to a dummy version of said selected reference signal in said gain mode and couples a second plate of said replica capacitor to said sample capacitor in said portion.