Display device

• US 7,414,607 B2
• Filed: 12/12/2003
• Issued: 08/19/2008
• Est. Priority Date: 12/13/2002
• Status: Expired due to Fees

• Current Assignee: Sharp Kabushiki Kaisha (Hon Hai Precision Industry Co., Ltd.)
• Original Assignee: Sharp Kabushiki Kaisha (Hon Hai Precision Industry Co., Ltd.)
• Inventors: Maeda, Kazuhiro, Washio, Hajime, Onda, Mamoru
• Primary Examiner(s): Awad; Amr
• Assistant Examiner(s): Sherman; Stephen G
• Application Number:
  US10/733,395
• Publication Number:
  US 20040119675A1
• Time in Patent Office: 1,712 Days
• Field of Search: 345/100, 345/87, 345 98- 99, 345/204
• US Class Current: 345/100
• CPC Class Codes: G09G 2300/043 Compensation electrodes or other additional electrodes in matrix displays related to distortions or compensation signals, e.g. for modifying TFT threshold voltage in column driver
• CPC Class Codes: G09G 2310/0248 Precharge or discharge of column electrodes before or after applying exact column voltages
• CPC Class Codes: G09G 2320/0223 Compensation for problems related to R-C delay and attenuation in electrodes of matrix panels, e.g. in gate electrodes or on-substrate video signal electrodes
• CPC Class Codes: G09G 2330/021 Power management, e.g. power saving
• CPC Class Codes: G09G 3/3607 for displaying colours or for displaying grey scales with a specific pixel layout, e.g. using sub-pixels display of colours in flat matrix panels other than liquid crystal displays G09G3/2003; grey scales specific for television H04N3/127
• CPC Class Codes: G09G 3/3677 suitable for active matrices only
• CPC Class Codes: G09G 3/3688 suitable for active matrices only

Abstract

In a structure in which a plurality of signals related to each other are supplied to a driving circuit in such a manner that at least one of the signals is supplied also to the other circuit, the present invention prevents change of phase relation between the plural signals due to difference in wiring load, without directly processing the signals with higher power consumption. The first and second clock signals SCK1 and SCK2 are supplied to the first data signal line driving circuit SD1, while the first clock signal SCK1 is also supplied to the second data signal line driving circuit SD2 in parallel. The wirings 1 and 2 for the respective signals are adjusted to have equal wiring load with a dummy wiring 2 provided in the wiring 2, for solving uneven wiring load caused by difference of leading manner, the dummy wiring 2 constituting an additional capacitor section 7, together with a liquid crystal layer and a counter electrode.

Claims

1. A display device, comprising:

a scanning signal line driving circuit for driving scanning signal lines;

a data signal line driving circuit for driving data signal lines intersecting the scanning signal lines,

at least one of the scanning signal line driving circuit and the data signal line driving circuit being supplied with at least first and second signals, the first signal being supplied in parallel to other circuit than the driving circuit supplied with the first and second signals,

the display device further comprising wiring load adjustment section for equalizing wiring load of the second signal which is supplied to the driving circuit, and wiring load of the first signal which is supplied in parallel to the driving circuit and the other circuit;

wherein;

the scanning signal lines and the data signal lines are formed on a substrate, and a liquid crystal layer is held between the substrate and a substrate having a counter electrode,

the wiring load adjustment section uses the liquid crystal layer as a dielectric substance, and is constituted of dummy wiring connected to the wiring of the second signal which is supplied to the driving circuit and a liquid crystal layer on the dummy wiring, and the counter electrode.

2. The display device as set forth in claim 1, wherein:

the other circuit is a circuit for driving the scanning signal lines or the data signal lines.

3. The display device as set forth in claim 1, wherein:

the first signal is supplied to the driving circuit and the other circuit from a common input terminal and through a common signal line.

4. The display device as set forth in claim 1, wherein:

the first and second signals are clock signals of plural systems, respectively.

5. The display device as set forth in claim 1, wherein:

the first and second signals are digital image signals constituted of a plurality of bits, and are divided into at least two bit groups.

6. The display device as set forth in claim 1, wherein:

the wiring load adjustment section adjusts time constants of the respective wirings of the first and second signals.

7. The display device as set forth in claim 1, wherein:

the dummy wiring is formed in a fanfold shape on a vacant area, which is an area holding the liquid crystal layer on the substrate having a counter electrode, and being provided as a part of a display section but is not involved in image display, the vacant area being closer to an end portion of the substrate than the data signal line driving circuit.

8. The display device as set forth in claim 1, wherein:

the dummy wiring is formed in a plate shape to be in parallel with the counter electrode.

9. The display device as set forth in claim 1, wherein:

the dummy wiring is formed in a periphery of a display section involved in image display.

10. The display device as set forth in claim 1, wherein:

the other circuit is a pre-charging circuit for carrying out pre-charging of the data signal lines.

11. The display device as set forth in claim 1, wherein:

the wiring load adjustment section is provided in the scanning signal line driving circuit.

12. A display device, comprising:

a scanning signal line driving circuit for driving scanning signal lines;

a data signal line driving circuit for driving data signal lines intersecting the scanning signal lines,

at least one of the scanning signal line driving circuit and the data signal line driving circuit being supplied with at least first and second signals, the first signal being supplied in parallel to other circuit than the driving circuit supplied with the first and second signals,

the display device further comprising wiring load adjustment section for equalizing wiring load of the second signal which is supplied to the driving circuit, and wiring load of the first signal which is supplied in parallel to the driving circuit and the other circuit;

wherein;

the scanning signal lines and the data signal lines are formed on a substrate where an interlayer insulation film and a conductive film are formed, and

the wiring load adjustment section uses the interlayer insulation film as a dielectric substance, and is constituted of dummy wiring connected to the wiring of the second signal supplied to the driving circuit, the interlayer insulation film, and the conductive film.

13. The display device as set forth in claim 12, wherein:

the dummy wiring is formed in a periphery of a display section involved in image display.

14. The display device as set forth in claim 12, wherein:

the other circuit is a circuit for driving the scanning signal lines or the data signal lines.

15. The display device as set forth in claim 12, wherein:

the first signal is supplied to the driving circuit and the other circuit from a common input terminal and through a common signal line.

16. The display device as set forth in claim 12, wherein:

the first and second signals are clock signals of plural systems, respectively.

17. The display device as set forth in claim 12, wherein:

the first and second signals are digital image signals constituted of a plurality of bits, and are divided into at least two bit groups.

18. The display device as set forth in claim 12, wherein:

the wiring load adjustment section adjusts time constants of the respective wirings of the first and second signals.

19. A display device, comprising:

a scanning signal line driving circuit for driving scanning signal lines;

a data signal line driving circuit for driving data signal lines intersecting the scanning signal lines,

at least one of the scanning signal line driving circuit and the data signal line driving circuit being supplied with at least first and second signals, the first signal being supplied in parallel to other circuit than the driving circuit supplied with the first and second signals,

the display device further comprising wiring load adjustment section for equalizing wiring load of the second signal which is supplied to the driving circuit, and wiring load of the first signal which is supplied in parallel to the driving circuit and the other circuit;

wherein;

the scanning signal lines and the data signal lines have a thin film transistor for each intersection, and

the wiring load adjustment section uses layers for constituting a gate insulation film of a thin film transistor as a dielectric substance, and is constituted of dummy wiring connected to the wiring of the second signal supplied to the driving circuit, and layers for constituting a gate insulation film and a semiconductor layer of a thin film transistor stacked on the dummy wiring.

20. The display device as set forth in claim 19, wherein:

the dummy wiring is formed in a periphery of a display section involved in image display.

21. The display device as set forth in claim 19, wherein:

the other circuit is a circuit for driving the scanning signal lines or the data signal lines.

22. The display device as set forth in claim 19, wherein:

the first signal is supplied to the driving circuit and the other circuit from a common input terminal and through a common signal line.

23. The display device as set forth in claim 19, wherein:

the first and second signals are clock signals of plural systems, respectively.

24. The display device as set forth in claim 19, wherein:

the first and second signals are digital image signals constituted of a plurality of bits, and are divided into at least two bit groups.

25. The display device as set forth in claim 19, wherein:

the wiring load adjustment section adjusts time constants of the respective wirings of the first and second signals.