Apparatus and methods for a physical layout of simultaneously sub-accessible memory modules
First Claim
1. A memory module having a memory interface, comprising:
- a plurality of memory devices organized into at least four memory ranks, each memory rank having a set of memory devices being electrically isolated from each other, at least one memory rank being located on a first side of the memory module and at least another memory rank being located on a second side of the memory module; and
at least four drivers, each respective drivers operatively coupled to at least one of the memory devices in a respective one of the memory ranks, the driver being adapted to be coupled to the memory interface, wherein the memory ranks are either individually or simultaneously, or both individually and simultaneously accessible by the driver so that one or more memory devices in one or more memory ranks may be accessed at one time.
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Abstract
A layout for simultaneously sub-accessible memory modules is disclosed. In one embodiment, a memory module includes a printed circuit board having a plurality of sectors, each sector being electrically isolated from the other sectors and having a multi-layer structure. At least one memory device is attached to each sector, the memory devices being organized into a plurality of memory ranks. A driver is attached to the printed circuit board and is operatively coupled to the memory ranks. The driver is adapted to be coupled to a memory interface of the computer system. Because the sectors are electrically-isolated from adjacent sectors, the memory ranks are either individually or simultaneously, or both individually and simultaneously accessible by the driver so that one or more memory devices on a particular sector may be accessed at one time. In an alternate embodiment, the printed circuit board includes a driver sector electrically isolated from the other sectors and having a multi-layer structure, the driver being attached to the driver sector.
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Citations
82 Claims
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1. A memory module having a memory interface, comprising:
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a plurality of memory devices organized into at least four memory ranks, each memory rank having a set of memory devices being electrically isolated from each other, at least one memory rank being located on a first side of the memory module and at least another memory rank being located on a second side of the memory module; and at least four drivers, each respective drivers operatively coupled to at least one of the memory devices in a respective one of the memory ranks, the driver being adapted to be coupled to the memory interface, wherein the memory ranks are either individually or simultaneously, or both individually and simultaneously accessible by the driver so that one or more memory devices in one or more memory ranks may be accessed at one time. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
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11. A computer system, comprising:
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a central processing unit; a system memory; a bus bridge coupled to the central processing unit and the system memory and adapted to allow communication between the central processing unit and the system memory, wherein the system memory includes at least one memory module comprising; a plurality of memory devices organized into at least two memory ranks, each memory rank having a set of memory devices being electrically isolated from each other; and at least one driver operatively coupled to at least one of the memory devices in a respective one of the memory ranks and to the bus bridge, wherein the memory ranks are either individually or simultaneously, or both individually and simultaneously accessible by the driver so that one or more memory devices in one or more memory ranks may be accessed at one time. - View Dependent Claims (12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24)
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25. A method of accessing and processing data in a system memory coupled to a data bus of a computer system, comprising:
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providing a memory module having a plurality of memory devices divided into a plurality of memory ranks, each memory rank comprising a set memory devices being electrically-isolated; receiving a plurality of command signals and a plurality of address signals into a plurality of driver chips via the bus; processing the plurality of command signals and plurality of address signals; and simultaneously accessing two or more memory devices of one or more memory rank based on the plurality of command signals and plurality of address signals. - View Dependent Claims (26, 27, 28, 29, 30, 31, 32, 33, 34)
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35. A memory module having a memory interface, comprising:
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a plurality of memory devices organized into at least two memory ranks, each memory rank having a set of memory devices being electrically isolated from each other; a driver sector electrically isolated from the at least two memory ranks; and at least one driver coupled to the driver sector and operatively coupled to at least one of the memory devices in a respective one of the memory ranks, the driver being adapted to be coupled to the memory interface, wherein the memory ranks are either individually or simultaneously, or both individually and simultaneously accessible by the driver so that one or more memory devices in one or more memory ranks may be accessed at one time. - View Dependent Claims (36, 37, 38, 39, 40, 41, 42, 43, 44)
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45. A memory module having a memory interface, comprising:
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a plurality of memory devices organized into at least four memory ranks, each memory rank having at least four memory devices being electrically isolated from each other; and a single driver operatively coupled to at least one of the memory devices in a respective one of the memory ranks, the driver being adapted to be coupled to the memory interface, wherein the memory ranks are either individually or simultaneously, or both individually and simultaneously accessible by the driver so that one or more memory devices in one or more memory ranks may be accessed at one time. - View Dependent Claims (46, 47, 48, 49, 50, 51, 52, 53)
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54. A memory module having a memory interface, comprising:
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a plurality of memory devices organized into at least two memory ranks, each memory rank having a set of memory devices being electrically isolated from each other; and at least one driver operatively coupled to at least one of the memory devices in a respective one of the memory ranks, the driver being adapted to be coupled to receive optical signals from the memory interface, wherein the memory ranks are either individually or simultaneously, or both individually and simultaneously accessible by the driver so that one or more memory devices in one or more memory ranks may be accessed at one time. - View Dependent Claims (55, 56, 57)
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58. A memory module having a memory interface, comprising:
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a plurality of memory devices organized into at least two memory ranks, each memory rank having a set of memory devices being electrically isolated from each other; and at least one driver operatively coupled to at least one of the memory devices in a respective one of the memory ranks, the driver being adapted to be coupled to receive RF signals from the memory interface, wherein the memory ranks are either individually or simultaneously, or both individually and simultaneously accessible by the driver so that one or more memory devices in one or more memory ranks may be accessed at one time. - View Dependent Claims (59, 60, 61)
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62. A method of accessing and processing data in a system memory coupled to a data bus of a computer system, comprising:
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providing a memory module having a plurality of memory devices divided into a plurality of memory ranks, each memory rank comprising a set memory devices being electrically-isolated; receiving a plurality of command signals and a plurality of address signals via the bus; processing the plurality of command signals and plurality of address signals; and simultaneously writing to two or more memory devices of one or more memory rank based on the plurality of command signals and plurality of address signals. - View Dependent Claims (63, 64, 65, 66, 67, 68)
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69. A method of accessing and processing data in a system memory coupled to a data bus of a computer system, comprising:
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providing a memory module having a plurality of memory devices divided into a plurality of memory ranks, each memory rank comprising a set memory devices being electrically-isolated; receiving a plurality of command signals and a plurality of address signals via the bus; processing the plurality of command signals and plurality of address signals; and simultaneously reading from two or more memory devices of one or more memory rank based on the plurality of command signals and plurality of address signals. - View Dependent Claims (70, 71, 72, 73, 74)
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75. A method of accessing and processing data in a system memory coupled to a data bus of a computer system, comprising:
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providing a memory module having a plurality of memory devices divided into a plurality of memory ranks, each memory rank comprising a set memory devices being electrically-isolated; receiving a plurality of command signals and a plurality of address signals via the bus, wherein the signals include a plurality of optical signals; processing the plurality of command signals and plurality of address signals; and simultaneously accessing two or more memory devices of one or more memory rank based on the plurality of command signals and plurality of address signals. - View Dependent Claims (76, 77, 78)
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79. A method of accessing and processing data in a system memory coupled to a data bus of a computer system, comprising:
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providing a memory module having a plurality of memory devices divided into a plurality of memory ranks, each memory rank comprising a set memory devices being electrically-isolated; receiving a plurality of command signals and a plurality of address signals via the bus, wherein the signals include a plurality of RF signals; processing the plurality of command signals and plurality of address signals; and simultaneously accessing two or more memory devices of one or more memory rank based on the plurality of command signals and plurality of address signals. - View Dependent Claims (80, 81, 82)
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Specification