Semiconductor memory device

• US 7,414,879 B2
• Filed: 12/22/2005
• Issued: 08/19/2008
• Est. Priority Date: 10/21/2005
• Status: Active Grant

• Current Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Asao, Yoshiaki, Nitayama, Akihiro
• Primary Examiner(s): Dinh; Son
• Assistant Examiner(s): NGUYEN, NAM THANH
• Application Number:
  US11/313,847
• Publication Number:
  US 20070091673A1
• Time in Patent Office: 971 Days
• Field of Search: 365/158, 365/171, 365/173
• US Class Current: 365/158
• CPC Class Codes: G11C 11/16 using elements in which the storage effect is based on magnetic spin effect

Abstract

A semiconductor memory device includes a memory cell block including a plurality of memory cells connected in series between first node and second node, the memory cells including a magnetoresistive element and a switching transistor, which are connected in parallel, the magnetoresistive element being a spin injection type and including a fixed layer whose magnetization direction is fixed, a recording layer whose magnetization direction changes, and a non-magnetic layer interposed between the fixed layer and the recording layer, a bit line connected to the first node via a selection transistor, a word line connected to a gate of the switching transistor, and a write line connected to the second node.

Claims

1. A semiconductor memory device comprising:

a memory cell block including a plurality of memory cells connected in series between first node and second node, the memory cells including a magnetoresistive element and a switching transistor, which are connected in parallel, the magnetoresistive element being a spin injection type and including a fixed layer whose magnetization direction is fixed, a recording layer whose magnetization direction changes, and a non-magnetic layer interposed between the fixed layer and the recording layer;

a bit line connected to the first node via a selection transistor;

a word line connected to a gate of the switching transistor;

a write line connected to the second node; and

a top electrode and bottom electrode provided via the magnetoresistive element,

wherein the top electrode and the bottom electrode supply a current perpendicular to a plane to the magnetoresistive element, and the magnetization direction of the recording layer changes by spin-polarized electrons included in the current.

2. The semiconductor memory device according to claim 1, wherein to write data in the memory cells, the memory cell block is supplied with a current flowing from the first node to the second node or from the second node to the first node via the bit line and the write line.

3. The semiconductor memory device according to claim 1, further comprising:

a selection line connected to a gate of the selection transistor.

4. The semiconductor memory device according to claim 1, wherein the magnetoresistive elements of the memory cells are arranged along a first direction,

a first pair of two neighboring magnetoresistive elements share the bottom electrode,

a second pair of two neighboring magnetoresistive elements share the top electrode, and

the first pair and the second pair share a magnetoresistive element.

5. The semiconductor memory device according to claim 4, wherein the switching transistor includes:

a gate electrode provided on a semiconductor substrate via a gate insulating film to extend to a second direction perpendicular to the first direction, and corresponding to the word line; and

source/drain regions provided on both sides of the gate electrode in the semiconductor substrate, and

two neighboring switching transistors share a source/drain region.

6. The semiconductor memory device according to claim 5, wherein the magnetoresistive element is arranged over the gate electrode.

7. The semiconductor memory device according to claim 4, wherein the magnetoresistive element is circular or square in its plane.

8. The semiconductor memory device according to claim 4, wherein the bit line extends to the first direction, and is arranged above the top electrode.

9. The semiconductor memory device according to claim 5, further comprising:

a first contact plug corresponding to the bottom electrode, and connecting the bottom electrode to one of the source/drain regions; and

a second contact plug corresponding to the top electrode, and connecting the top electrode to one of the source/drain regions.

10. The semiconductor memory device according to claim 1, wherein the recording layer comprises a ferromagnetic material, and the fixed layer comprises a layer stacking a ferromagnetic material and a anti-ferromagnetic materials.