Decoder design adaptable to decode coded signals using min* or max* processing

• US 7,415,079 B2
• Filed: 06/10/2004
• Issued: 08/19/2008
• Est. Priority Date: 09/12/2000
• Status: Expired due to Fees

• Current Assignee: Broadcom Corporation (Broadcom, Inc.)
• Original Assignee: Broadcom Corporation (Broadcom, Inc.)
• Inventors: Shen, Ba-Zhong, Tran, Hau Thien, Cameron, Kelly Brian
• Primary Examiner(s): Ghayour; Mohammad H.
• Assistant Examiner(s): Williams; Lawrence B
• Application Number:
  US10/865,456
• Publication Number:
  US 20040240590A1
• Time in Patent Office: 1,531 Days
• Field of Search: 375/340, 375/341, 375/262, 375/265, 714/724, 714/755, 714/794, 714/795, 714/796, 714/780, 714/801, 714/781
• US Class Current: 375/340
• CPC Class Codes: H03M 13/1102 Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes
• CPC Class Codes: H03M 13/258 with turbo codes, e.g. Turbo Trellis Coded Modulation [TTCM]
• CPC Class Codes: H03M 13/275 Interleaver wherein the permutation pattern is obtained using a congruential operation of the type y=ax+b modulo c
• CPC Class Codes: H03M 13/2906 using block codes H03M13/2957 takes precedence
• CPC Class Codes: H03M 13/2939 using convolutional codes H03M13/2957 takes precedence
• CPC Class Codes: H03M 13/2957 Turbo codes and decoding
• CPC Class Codes: H03M 13/3922 Add-Compare-Select [ACS] operation in forward or backward recursions
• CPC Class Codes: H03M 13/3927 Log-Likelihood Ratio [LLR] computation by combination of forward and backward metrics into LLRs
• CPC Class Codes: H03M 13/4107 implementing add, compare, select [ACS] operations
• CPC Class Codes: H04L 1/005 Iterative decoding, including iteration between signal detection and decoding operation
• CPC Class Codes: H04L 1/006 Trellis-coded modulation
• CPC Class Codes: H04L 1/0065 Serial concatenated codes
• CPC Class Codes: H04L 1/0066 Parallel concatenated codes
• CPC Class Codes: H04L 1/0071 Use of interleaving interleaving per se H03M13/27

Abstract

Decoder design adaptable to decode coded signals using min* or max* processing. A very efficient means of min* processing or max* processing may be performed within a communication device to assist in the very complex and cumbersome calculations that are employed when decoding coded signals. The types of coded signals that may be decoded using min* processing or max* processing are varied, and they include LDPC (Low Density Parity Check) coded signals, turbo coded signals, and TTCM (Turbo Trellis Coded Modulation) coded signals, among other coded signal types. Many of the calculations and/or determinations performed within min* processing or max* processing are performed simultaneously and in parallel of one another thereby ensuring very fast operation. In a finite precision digital implementation, when certain calculated bits of min* or max* processing are available, they govern selection of resultants from among multiple calculations and determinations made simultaneously and in parallel.

Claims

1. A min* (min star) circuit, the circuit comprising:

a subtraction block that is operable to calculate a difference between a first input value and a second input value;

a first log correction factor block that is operable to determine a first log correction factor based on a first plurality of LSBs (Least Significant Bits) of the difference;

a second log correction factor block that is operable to determine a second log correction factor based on the first plurality of LSBs of the difference;

a min* log saturation block whose output value is governed by a second plurality of LSBs of the difference;

a log correction factor MUX (Multiplexor) that is operable to receive the first log correction factor and the second log correction factor as inputs and whose selection is governed by an MSB (Most Significant Bit) of the second plurality of LSBs of the difference;

an input value selection MUX that is operable to receive the first input value and the second input value as inputs and whose selection is governed by an MSB of the difference; and

a logic OR gate that is operable to receive the output value from the min* log saturation block and an output of the log correction factor MUX; and

wherein;

an output of the input value selection MUX is a minimum input value selected from among the first input value and the second input value; and

an output of the logic OR gate is a final log correction factor;

the first input value is a finite precision number A;

the second input value is a finite precision number B;

in accordance with min* processing, the minimum input value is A or B; and

in accordance with min* processing, the final log correction factor is ln(1+e<sup>−

|A−

B|</sup>).

2. The circuit of claim 1, wherein:

the final log correction factor is subtracted from the minimum input value to generate a final min* resultant based on the first input value and the second input value.

3. The circuit of claim 1, wherein:

the final log correction factor is subtracted from the minimum input value to generate an intermediate min* resultant based on the first input value and the second input value; and

a constant value offset is added to the intermediate min* resultant to generate a final min* resultant based on the first input value and the second input value.

4. The circuit of claim 1, wherein:

the MSB of the difference is a sign bit of the difference.

5. The circuit of claim 1, wherein:

during a first time period;

the subtraction block is operable to calculate the first plurality of LSBs of the difference between the first input value and the second input value;

during a second time period;

the subtraction block is operable to calculate the second plurality of LSBs of the difference between the first input value and the second input value;

the first log correction factor block is operable to determine the first log correction factor based on the first plurality of LSBs of the difference; and

the second log correction factor block is operable to determine the second log correction factor based on the first plurality of LSBs of the difference.

6. The circuit of claim 1, wherein:

during a first time period;

the subtraction block is operable to calculate the first plurality of LSBs of the difference between the first input value and the second input value;

during a second time period;

the subtraction block is operable to calculate the second plurality of LSBs of the difference between the first input value and the second input value;

the first log correction factor block is operable to determine the first log correction factor based on the first plurality of LSBs of the difference;

the second log correction factor block is operable to determine the second log correction factor based on the first plurality of LSBs of the difference;

during a third time period; and

the MSB of the second plurality of LSBs of the difference directs the log correction factor MUX select either the first log correction factor or the second log correction factor.

7. The circuit of claim 1, further comprising:

a LUT (Look-Up Table) that includes a plurality of first log correction factors and a plurality of second log correction factors defined as a function of first plurality of LSBs of the difference;

wherein the first log correction factor block looks up the first log correction factor from the LUT based on the first plurality of LSBs of the difference; and

wherein the second log correction factor block looks up the second log correction factor from the LUT based on the first plurality of LSBs of the difference.

8. The circuit of claim 1, further comprising:

a LUT (Look-Up Table) that includes a plurality of first log correction factors and a plurality of second log correction factors defined as a function of first plurality of LSBs of the difference;

wherein the first log correction factor block looks up the first log correction factor from the LUT based on the first plurality of LSBs of the difference;

wherein the second log correction factor block looks up the second log correction factor from the LUT based on the first plurality of LSBs of the difference; and

wherein each log correction factor of the plurality of first log correction factors and a plurality of second log correction factors is bit value of either a 0 or a 1 as defined by a single bit of precision.

9. The circuit of claim 1, further comprising:

a LUT (Look-Up Table) that includes a plurality of min* log saturation block output values defined as a function of the second plurality of LSBs of the difference.

10. The circuit of claim 1, wherein:

the output value of the min* log saturation block is a 1 when each bit of the second plurality of LSBs of the difference is a 1;

the output value of the min* log saturation block is a 1 when each bit of the second plurality of LSBs of the difference is a 0; and

the output value of the min* log saturation block is a 0 when at least one bit of the second plurality of LSBs of the difference is a 1 and at least one bit of the second plurality of LSBs of the difference is a 0.

11. The circuit of claim 1, wherein:

the final log correction factor is a bit value of either a 0 or a 1 as defined by a single bit of precision.

12. The circuit of claim 1, wherein:

the circuit is contained within an LDPC (Low Density Parity Check) decoder that is operable to decode an LDPC coded signal.

13. The circuit of claim 1, wherein:

the circuit is contained within a MAP decoder that is operable to decode a turbo coded signal or a TTCM (Turbo Trellis Coded Modulation) coded signal.

14. The circuit of claim 1, wherein:

the circuit is contained within a decoder that is operable to decode a coded signal;

the decoder is implemented within a communication device; and

the communication device is implemented within at least one of a cable television distribution system, a satellite communication system, an HDTV (High Definition Television) communication system, a cellular communication system, a microwave communication system, a point-to-point communication system, a uni-directional communication system, a bi-directional communication system, a one to many communication system, a fiber-optic communication system, a WLAN (Wireless Local Area Network) communication system, and a DSL (Digital Subscriber Line) communication system.

84. The method of claim 3, further comprising:

looking up the first log correction factor within a LUT (Look-Up Table) based on the first plurality of LSBs of the difference;

looking up the second log correction factor within the LUT based on the first plurality of LSBs of the difference; and

wherein the LUT includes a plurality of first log correction factors and a plurality of second log correction factors defined as a function of first plurality of LSBs of the difference.

15. A min* (min star) circuit, the circuit comprising:

a subtraction block that is operable to calculate a difference between a first input value and a second input value;

a first log correction factor block that is operable to determine a first log correction factor based on a first plurality of LSBs (Least Significant Bits) of the difference;

a second log correction factor block that is operable to determine a second log correction factor based on the first plurality of LSBs of the difference;

a min* log saturation block whose output value is governed by a second plurality of LSBs of the difference;

a log correction factor MUX (Multiplexor) that is operable to receive the first log correction factor and the second log correction factor as inputs and whose selection is governed by an MSB (Most Significant Bit) of the second plurality of LSBs of the difference;

an input value selection MUX that is operable to receive the first input value and the second input value as inputs and whose selection is governed by an MSB of the difference; and

a logic OR gate that is operable to receive the output value from the min* log saturation block and an output of the log correction factor MUX; and

wherein;

an output of the input value selection MUX is a minimum input value selected from among the first input value and the second input value;

an output of the logic OR gate is a final log correction factor;

during a first time period;

the subtraction block is operable to calculate the first plurality of LSBs of the difference between the first input value and the second input value;

during a second time period;

the subtraction block is operable to calculate the second plurality of LSBs of the difference between the first input value and the second input value;

the first log correction factor block is operable to determine the first log correction factor based on the first plurality of LSBs of the difference; and

the second log correction factor block is operable to determine the second log correction factor based on the first plurality of LSBs of the difference;

the first input value is a finite precision number A;

the second input value is a finite precision number B;

in accordance with min* processing, the minimum input value is A or B; and

in accordance with min*processing, the final log correction factor is ln(1+e<sup>−

|A−

B|</sup>).

16. The circuit of claim 15, wherein:

the final log correction factor is subtracted from the minimum input value to generate a final min* resultant based on the first input value and the second input value.

17. The circuit of claim 15, wherein:

the final log correction factor is subtracted from the minimum input value to generate an intermediate min* resultant based on the first input value and the second input value; and

a constant value offset is added to the intermediate min* resultant to generate a final min* resultant based on the first input value and the second input value.

18. The circuit of claim 15, wherein:

the MSB of the difference is a sign bit of the difference.

19. The circuit of claim 15, wherein:

during a third time period; and

the MSB of the second plurality of LSBs of the difference directs the log correction factor MUX select either the first log correction factor or the second log correction factor.

20. The circuit of claim 15, further comprising:

a LUT (Look-Up Table) that includes a plurality of first log correction factors and a plurality of second log correction factors defined as a function of first plurality of LSBs of the difference;

wherein the first log correction factor block looks up the first log correction factor from the LUT based on the first plurality of LSBs of the difference; and

wherein the second log correction factor block looks up the second log correction factor from the LUT based on the first plurality of LSBs of the difference.

21. The circuit of claim 15, further comprising:

a LUT (Look-Up Table) that includes a plurality of first log correction factors and a plurality of second log correction factors defined as a function of first plurality of LSBs of the difference;

wherein the first log correction factor block looks up the first log correction factor from the LUT based on the first plurality of LSBs of the difference;

wherein the second log correction factor block looks up the second log correction factor from the LUT based on the first plurality of LSBs of the difference; and

wherein each log correction factor of the plurality of first log correction factors and a plurality of second log correction factors is bit value of either a 0 or a 1 as defined by a single bit of precision.

22. The circuit of claim 15, further comprising:

a LUT (Look-Up Table) that includes a plurality of min* log saturation block output values defined as a function of the second plurality of LSBs of the difference.

23. The circuit of claim 15, wherein:

the output value of the min* log saturation block is a 1 when each bit of the second plurality of LSBs of the difference is a 1;

the output value of the min* log saturation block is a 1 when each bit of the second plurality of LSBs of the difference is a 0; and

the output value of the min* log saturation block is a 0 when at least one bit of the second plurality of LSBs of the difference is a 1 and at least one bit of the second plurality of LSBs of the difference is a 0.

24. The circuit of claim 15, wherein:

the final log correction factor is a bit value of either a 0 or a 1 as defined by a single bit of precision.

25. The circuit of claim 15, wherein:

the circuit is contained within an LDPC (Low Density Parity Check) decoder that is operable to decode an LDPC coded signal.

26. The circuit of claim 15, wherein:

the circuit is contained within a MAP decoder that is operable to decode a turbo coded signal or a TTCM (Turbo Trellis Coded Modulation) coded signal.

27. The circuit of claim 15, wherein:

the circuit is contained within a decoder that is operable to decode a coded signal;

the decoder is implemented within a communication device; and

the communication device is implemented within at least one of a cable television distribution system, a satellite communication system, an HDTV (High Definition Television) communication system, a cellular communication system, a microwave communication system, a point-to-point communication system, a uni-directional communication system, a bi-directional communication system, a one to many communication system, a fiber-optic communication system, a WLAN (Wireless Local Area Network) communication system, and a DSL (Digital Subscriber Line) communication system.

28. A min* (min star) circuit, the circuit comprising:

a subtraction block that is operable to calculate a difference between a first input value and a second input value;

a first log correction factor block that is operable to determine a first log correction factor based on a first plurality of LSBs (Least Significant Bits) of the difference;

a second log correction factor block that is operable to determine a second log correction factor based on the first plurality of LSBs of the difference;

a min* log saturation block whose output value is governed by a second plurality of LSBs of the difference;

a log correction factor MUX (Multiplexor) that is operable to receive the first log correction factor and the second log correction factor as inputs and whose selection is governed by an MSB (Most Significant Bit) of the second plurality of LSBs of the difference;

an input value selection MUX that is operable to receive the first input value and the second input value as inputs and whose selection is governed by an MSB of the difference;

a logic OR gate that is operable to receive the output value from the min* log saturation block and an output of the log correction factor MUX, wherein;

an output of the input value selection MUX is a minimum input Value selected from among the first input value and the second input value; and

an output of the logic OR gate is a final log correction factor; and

a LUT (Look-Up Table) that includes a plurality of first log correction factors and a plurality of second log correction factors defined as a function of first plurality of LSBs of the difference; and

wherein;

the first log correction factor block looks up the first log correction factor from the LUT based on the first plurality of LSBs of the difference;

the second log correction factor block looks up the second log correction factor from the LUT based on the first plurality of LSBs of the difference;

each log correction factor of the plurality of first log correction factors and a plurality of second log correction factors is bit value of either a 0 or a 1 as defined by a single bit of precision;

the output value of the min* log saturation block is a 1 when each bit of the second plurality of LSBs of the difference is a 1;

the output value of the min* log saturation block is a 1 when each bit of the second plurality of LSBs of the difference is a 0;

the output value of the min* log saturation block is a 0 when at least one bit of the second plurality of LSBs of the difference is a 1 and at least one bit of the second plurality of LSBs of the difference is a 0; and

the final log correction factor is a bit value of either a 0 or a 1 as defined by a single bit of precision;

the first input value is a finite precision number A;

the second input value is a finite precision number B;

in accordance with min* processing, the minimum input value is A or B; and

in accordance with min* processing, the final log correction factor is ln(1+e<sup>−

|A−

B|</sup>).

29. The circuit of claim 28, wherein:

the final log correction factor is subtracted from the minimum input value to generate a final min* resultant based on the first input value and the second input value.

30. The circuit of claim 28, wherein:

the final log correction factor is subtracted from the minimum input value to generate an intermediate min* resultant based on the first input value and the second input value; and

a constant value offset is added to the intermediate min* resultant to generate a final min* resultant based on the first input value and the second input value.

31. The circuit of claim 28, wherein:

the MSB of the difference is a sign bit of the difference.

32. The circuit of claim 28, wherein:

during a first time period;

the subtraction block is operable to calculate the first plurality of LSBs of the difference between the first input value and the second input value;

during a second time period;

the subtraction block is operable to calculate the second plurality of LSBs of the difference between the first input value and the second input value;

the first log correction factor block is operable to determine the first log correction factor based on the first plurality of LSBs of the difference; and

the second log correction factor block is operable to determine the second log correction factor based on the first plurality of LSBs of the difference.

33. The circuit of claim 28, wherein:

during a first time period;

the subtraction block is operable to calculate the first plurality of LSBs of the difference between the first input value and the second input value;

during a second time period;

the subtraction block is operable to calculate the second plurality of LSBs of the difference between the first input value and the second input value;

the first log correction factor block is operable to determine the first log correction factor based on the first plurality of LSBs of the difference;

the second log correction factor block is operable to determine the second log correction factor based on the first plurality of LSBs of the difference;

during a third time period; and

the MSB of the second plurality of LSBs of the difference directs the log correction factor MUX select either the first log correction factor or the second log correction factor.

34. The circuit of claim 28, wherein:

the circuit is contained within an LDPC (Low Density Parity Check) decoder that is operable to decode an LDPC coded signal.

35. The circuit of claim 28, wherein:

the circuit is contained within a MAP decoder that is operable to decode a turbo coded signal or a TTCM (Turbo Trellis Coded Modulation) coded signal.

36. The circuit of claim 28, wherein:

the circuit is contained within a decoder that is operable to decode a coded signal;

the decoder is implemented within a communication device; and

the communication device is implemented within at least one of a cable television distribution system, a satellite communication system, an HDTV (High Definition Television) communication system, a cellular communication system, a microwave communication system, a point-to-point communication system, a uni-directional communication system, a bi-directional communication system, a one to many communication system, a fiber-optic communication system, a WLAN (Wireless Local Area Network) communication system, and a DSL (Digital Subscriber Line) communication system.

37. A max* (max star) circuit, the circuit comprising:

a subtraction block that is operable to calculate a difference between a first input value and a second input value;

a first log correction factor block that is operable to determine a first log correction factor based on a first plurality of LSBs (Least Significant Bits) of the difference;

a second log correction factor block that is operable to determine a second log correction factor based on the first plurality of LSBs of the difference;

a max* log saturation block whose output value is governed by a second plurality of LSBs of the difference;

a log correction factor MUX (Multiplexor) that is operable to receive the first log correction factor and the second log correction factor as inputs and whose selection is governed by an MSB (Most Significant Bit) of the second plurality of LSBs of the difference;

an input value selection MUX that is operable to receive the first input value and the second input value as inputs and whose selection is governed by an MSB of the difference; and

a logic AND gate that is operable to receive the output value from the max* log saturation block and an output of the log correction factor MUX; and

wherein;

an output of the input value selection MUX is a maximum input value selected from among the first input value and the second input value; and

an output of the logic AND gate is a final log correction factor;

the first input value is a finite precision number A;

the second input value is a finite precision number B;

in accordance with min* processing, the minimum input value is A or B; and

in accordance with min* processing, the final log correction factor is ln(1+e<sup>−

|A−

B|</sup>).

38. The circuit of claim 37, wherein:

the final log correction factor is added to the maximum input value to generate a final max* resultant based on the first input value and the second input value.

39. The circuit of claim 37, wherein:

the final log correction factor is added to the maximum input value to generate an intermediate max* resultant based on the first input value and the second input value; and

a constant value offset is added to the intermediate max* resultant to generate a final max* resultant based on the first input value and the second input value.

40. The circuit of claim 37, wherein:

the MSB of the difference is a sign bit of the difference.

41. The circuit of claim 37, wherein:

during a first time period;

the subtraction block is operable to calculate the first plurality of LSBs of the difference between the first input value and the second input value;

during a second time period;

the subtraction block is operable to calculate the second plurality of LSBs of the difference between the first input value and the second input value;

the first log correction factor block is operable to determine the first log correction factor based on the first plurality of LSBs of the difference; and

the second log correction factor block is operable to determine the second log correction factor based on the first plurality of LSBs of the difference.

42. The circuit of claim 37, wherein:

during a first time period;

the subtraction block is operable to calculate the first plurality of LSBs of the difference between the first input value and the second input value;

during a second time period;

the subtraction block is operable to calculate the second plurality of LSBs of the difference between the first input value and the second input value;

the first log correction factor block is operable to determine the first log correction factor based on the first plurality of LSBs of the difference;

the second log correction factor block is operable to determine the second log correction factor based on the first plurality of LSBs of the difference;

during a third time period; and

the MSB of the second plurality of LSBs of the difference directs the log correction factor MUX select either the first log correction factor or the second log correction factor.

43. The circuit of claim 37, further comprising:

a LUT (Look-Up Table) that includes a plurality of first log correction factors and a plurality of second log correction factors defined as a function of first plurality of LSBs of the difference;

wherein the first log correction factor block looks up the first log correction factor from the LUT based on the first plurality of LSBs of the difference; and

wherein the second log correction factor block looks up the second log correction factor from the LUT based on the first plurality of LSBs of the difference.

44. The circuit of claim 37, further comprising:

a LUT (Look-Up Table) that includes a plurality of first log correction factors and a plurality of second log correction factors defined as a function of first plurality of LSBs of the difference;

wherein the first log correction factor block looks up the first log correction factor from the LUT based on the first plurality of LSBs of the difference;

wherein the second log correction factor block looks up the second log correction factor from the LUT based on the first plurality of LSBs of the difference; and

wherein each log correction factor of the plurality of first log correction factors and a plurality of second log correction factors is bit value of either a 0 or a 1 as defined by a single bit of precision.

45. The circuit of claim 37, further comprising:

a LUT (Look-Up Table) that includes a plurality of max* log saturation block output values defined as a function of the second plurality of LSBs of the difference.

46. The circuit of claim 37, wherein:

the output value of the max* log saturation block is a 1 when each bit of the second plurality of LSBs of the difference is a 1;

the output value of the max* log saturation block is a 1 when each bit of the second plurality of LSBs of the difference is a 0; and

the output value of the max* log saturation block is a 0 when at least one bit of the second plurality of LSBs of the difference is a 1 and at least one bit of the second plurality of LSBs of the difference is a 0.

47. The circuit of claim 37, wherein:

the final log correction factor is a bit value of either a 0 or a 1 as defined by a single bit of precision.

48. The circuit of claim 37, wherein:

the circuit is contained within an LDPC (Low Density Parity Check) decoder that is operable to decode an LDPC coded signal.

49. The circuit of claim 37, wherein:

the circuit is contained within a MAP decoder that is operable to decode a turbo coded signal or a TTCM (Turbo Trellis Coded Modulation) coded signal.

50. The circuit of claim 37, wherein:

the circuit is contained within a decoder that is operable to decode a coded signal;

the decoder is implemented within a communication device; and

the communication device is implemented within at least one of a cable television distribution system, a satellite communication system, an HDTV (High Definition Television) communication system, a cellular communication system, a microwave communication system, a point-to-point communication system, a uni-directional communication system, a bi-directional communication system, a one to many communication system, a fiber-optic communication system, a WLAN (Wireless Local Area Network) communication system, and a DSL (Digital Subscriber Line) communication system.

51. A max* (max star) circuit, the circuit comprising:

a subtraction block that is operable to calculate a difference between a first input value and a second input value;

a first log correction factor block that is operable to determine a first log correction factor based on a first plurality of LSBs (Least Significant Bits) of the difference;

a second log correction factor block that is operable to determine a second log correction factor based on the first plurality of LSBs of the difference;

a max* log saturation block whose output value is governed by a second plurality of LSBs of the difference;

a log correction factor MUX (Multiplexor) that is operable to receive the first log correction factor and the second log correction factor as inputs and whose selection is governed by an MSB (Most Significant Bit) of the second plurality of LSBs of the difference;

an input value selection MUX that is operable to receive the first input value and the second input value as inputs and whose selection is governed by an MSB of the difference; and

a logic AND gate that is operable to receive the output value from the max* log saturation block and an output of the log correction factor MUX; and

wherein;

an output of the input value selection MUX is a maximum input value selected from among the first input value and the second input value;

an output of the logic AND gate is a final log correction factor;

during a first time period;

the subtraction block is operable to calculate the first plurality of LSBs of the difference between the first input value and the second input value;

during a second time period;

the subtraction block is operable to calculate the second plurality of LSBs of the difference between the first input value and the second input value;

the first log correction factor block is operable to determine the first log correction factor based on the first plurality of LSBs of the difference; and

the second log correction factor block is operable to determine the second log correction factor based on the first plurality of LSBs of the difference;

the first input value is a finite precision number A;

the second input value is a finite precision number B;

in accordance with min* processing, the minimum input value is A or B; and

in accordance with min* processing, the final log correction factor is ln(1+e<sup>−

|A−

B|</sup>).

52. The circuit of claim 51, wherein:

the final log correction factor is added to the maximum input value to generate a final max* resultant based on the first input value and the second input value.

53. The circuit of claim 51, wherein:

the final log correction factor is added to the maximum input value to generate an intermediate max* resultant based on the first input value and the second input value; and

a constant value offset is added to the intermediate max* resultant to generate a final max* resultant based on the first input value and the second input value.

54. The circuit of claim 51, wherein:

the MSB of the difference is a sign bit of the difference.

55. The circuit of claim 51, wherein:

during a third time period; and

the MSB of the second plurality of LSBs of the difference directs the log correction factor MUX select either the first log correction factor or the second log correction factor.

56. The circuit of claim 51, further comprising:

a LUT (Look-Up Table) that includes a plurality of first log correction factors and a plurality of second log correction factors defined as a function of first plurality of LSBs of the difference;

wherein the first log correction factor block looks up the first log correction factor from the LUT based on the first plurality of LSBs of the difference; and

wherein the second log correction factor block looks up the second log correction factor from the LUT based on the first plurality of LSBs of the difference.

57. The circuit of claim 51, further comprising:

a LUT (Look-Up Table) that includes a plurality of first log correction factors and a plurality of second log correction factors defined as a function of first plurality of LSBs of the difference;

wherein the first log correction factor block looks up the first log correction factor from the LUT based on the first plurality of LSBs of the difference;

wherein the second log correction factor block looks up the second log correction factor from the LUT based on the first plurality of LSBs of the difference; and

wherein each log correction factor of the plurality of first log correction factors and a plurality of second log correction factors is bit value of either a 0 or a 1 as defined by a single bit of precision.

58. The circuit of claim 51, further comprising:

a LUT (Look-Up Table) that includes a plurality of max* log saturation block output values defined as a function of the second plurality of LSBs of the difference.

59. The circuit of claim 51, wherein:

the output value of the max* log saturation block is a 1 when each bit of the second plurality of LSBs of the difference is a 1;

the output value of the max* log saturation block is a 1 when each bit of the second plurality of LSBs of the difference is a 0; and

the output value of the max* log saturation block is a 0 when at least one bit of the second plurality of LSBs of the difference is a 1 and at least one bit of the second plurality of LSBs of the difference is a 0.

60. The circuit of claim 51, wherein:

the final log correction factor is a bit value of either a 0 or a 1 as defined by a single bit of precision.

61. The circuit of claim 51, wherein:

the circuit is contained within an LDPC (Low Density Parity Check) decoder that is operable to decode an LDPC coded signal.

62. The circuit of claim 51, wherein:

the circuit is contained within a MAP decoder that is operable to decode a turbo coded signal or a TTCM (Turbo Trellis Coded Modulation) coded signal.

63. The circuit of claim 51, wherein:

the circuit is contained within a decoder that is operable to decode a coded signal;

the decoder is implemented within a communication device; and

the communication device is implemented within at least one of a cable television distribution system, a satellite communication system, an HDTV (High Definition Television) communication system, a cellular communication system, a microwave communication system, a point-to-point communication system, a uni-directional communication system, a bi-directional communication system, a one to many communication system, a fiber-optic communication system, a WLAN (Wireless Local Area Network) communication system, and a DSL (Digital Subscriber Line) communication system.

64. A max* (max star) circuit, the circuit comprising:

a subtraction block that is operable to calculate a difference between a first input value and a second input value;

a first log correction factor block that is operable to determine a first log correction factor based on a first plurality of LSBs (Least Significant Bits) of the difference;

a second log correction factor block that is operable to determine a second log correction factor based on the first plurality of LSBs of the difference;

a max* log saturation block whose output value is governed by a second plurality of LSBs of the difference;

a log correction factor MUX (Multiplexor) that is operable to receive the first log correction factor and the second log correction factor as inputs and whose selection is governed by an MSB (Most Significant Bit) of the second plurality of LSBs of the difference;

an input value selection MUX that is operable to receive the first input value and the second input value as inputs and whose selection is governed by an MSB of the difference;

a logic AND gate that is operable to receive the output value from the max* log saturation block and an output of the log correction factor MUX, wherein;

an output of the input value selection MUX is a maximum input value selected from among the first input value and the second input value; and

an output of the logic AND gate is a final log correction factor; and

a LUT (Look-Up Table) that includes a plurality of first log correction factors and a plurality of second log correction factors defined as a function of first plurality of LSBs of the difference;

the first log correction factor block looks up the first log correction factor from the LUT based on the first plurality of LSBs of the difference;

the second log correction factor block looks up the second log correction factor from the LUT based on the first plurality of LSBs of the difference;

each log correction factor of the plurality of first log correction factors and a plurality of second log correction factors is bit value of either a 0 or a 1 as defined by a single bit of precision;

the output value of the max* log saturation block is a 1 when each bit of the second plurality of LSBs of the difference is a 1;

the output value of the max* log saturation block is a 1 when each bit of the second plurality of LSBs of the difference is a 0; and

the output value of the max* log saturation block is a 0 when at least one bit of the second plurality of LSBs of the difference is a 1 and at least one bit of the second plurality of LSBs of the difference is a 0; and

the final log correction factor is a bit value of either a 0 or a 1 as defined by a single bit of precision;

the first input value is a finite precision number A;

the second input value is a finite precision number B;

in accordance with min* processing, the minimum input value is A or B; and

in accordance with min* processing, the final log correction factor is ln(1+e<sup>−

|A−

B|</sup>).

65. The circuit of claim 64, wherein:

the final log correction factor is added to the maximum input value to generate a final max* resultant based on the first input value and the second input value.

66. The circuit of claim 64, wherein:

the final log correction factor is added to the maximum input value to generate an intermediate max* resultant based on the first input value and the second input value; and

a constant value offset is added to the intermediate max* resultant to generate a final max* resultant based on the first input value and the second input value.

67. The circuit of claim 64, wherein:

the MSB of the difference is a sign bit of the difference.

68. The circuit of claim 64, wherein:

during a first time period;

the subtraction block is operable to calculate the first plurality of LSBs of the difference between the first input value and the second input value;

during a second time period;

the subtraction block is operable to calculate the second plurality of LSBs of the difference between the first input value and the second input value;

the first log correction factor block is operable to determine the first log correction factor based on the first plurality of LSBs of the difference; and

the second log correction factor block is operable to determine the second log correction factor based on the first plurality of LSBs of the difference.

69. The circuit of claim 64, wherein:

during a first time period;

the subtraction block is operable to calculate the first plurality of LSBs of the difference between the first input value and the second input value;

during a second time period;

the subtraction block is operable to calculate the second plurality of LSBs of the difference between the first input value and the second input value;

the first log correction factor block is operable to determine the first log correction factor based on the first plurality of LSBs of the difference;

the second log correction factor block is operable to determine the second log correction factor based on the first plurality of LSBs of the difference;

during a third time period; and

the MSB of the second plurality of LSBs of the difference directs the log correction factor MUX select either the first log correction factor or the second log correction factor.

70. The circuit of claim 64, wherein:

the circuit is contained within an LDPC (Low Density Parity Check) decoder that is operable to decode an LDPC coded signal.

71. The circuit of claim 64, wherein:

the circuit is contained within a MAP decoder that is operable to decode a turbo coded signal or a TTCM (Turbo Trellis Coded Modulation) coded signal.

72. The circuit of claim 64, wherein:

the circuit is contained within a decoder that is operable to decode a coded signal;

the decoder is implemented within a communication device; and

the communication device is implemented within at least one of a cable television distribution system, a satellite communication system, an HDTV (High Definition Television) communication system, a cellular communication system, a microwave communication system, a point-to-point communication system, a uni-directional communication system, a bi-directional communication system, a one to many communication system, a fiber-optic communication system, a WLAN (Wireless Local Area Network) communication system, and a DSL (Digital Subscriber Line) communication system.

73. A method for performing min* (min star) processing, the method comprising:

during a first time period;

calculating a first plurality of LSBs (Least Significant Bits) of a difference between a first input value and a second input value;

during a second time period;

calculating a second plurality of LSBs of the difference between the first input value and the second input value;

determining a first log correction factor based on the first plurality of LSBs of the difference;

determining a second log correction factor based on the first plurality of LSBs of the difference;

during a third time period;

selecting either the first log correction factor or the second log correction factor as being a final log correction value based on an MSB (Most Significant Bit) of the second plurality of LSBs of the difference; and

selecting a minimum input value from among the first input value and the second input value based on an MSB of the difference; and

wherein;

the first input value is a finite precision number A;

the second input value is a finite precision number B;

in accordance with min* processing, the minimum input value is A or B; and

in accordance with min* processing, the final log correction factor is ln(1+e<sup>−

|A−

B|</sup>).

74. The method of claim 73, further comprising:

looking up the first log correction factor within a LUT (Look-Up Table) based on the first plurality of LSBs of the difference;

looking up the second log correction factor within the LUT based on the first plurality of LSBs of the difference; and

wherein the LUT includes a plurality of first log correction factors and a plurality of second log correction factors defined as a function of first plurality of LSBs of the difference.

75. The method of claim 73, further comprising:

looking up the first log correction factor within a LUT (Look-Up Table) based on the first plurality of LSBs of the difference;

looking up the second log correction factor within the LUT based on the first plurality of LSBs of the difference;

wherein the LUT includes a plurality of first log correction factors and a plurality of second log correction factors defined as a function of first plurality of LSBs of the difference; and

wherein each log correction factor of the plurality of first log correction factors and a plurality of second log correction factors is bit value of either a 0 or a 1 as defined by a single bit of precision.

76. The method of claim 73, further comprising:

forcing the final log correction value to a predetermined value when each bit of the second plurality of LSBs of the difference is a 1 or when each bit of the second plurality of LSBs of the difference is a 0.

77. The method of claim 73, further comprising:

subtracting the final log correction factor from the minimum input value thereby generating a final min* resultant based on the first input value and the second input value.

78. The method of claim 73, further comprising:

subtracting the final log correction factor from the minimum input value thereby generating an intermediate min* resultant based on the first input value and the second input value; and

adding a constant value offset to the intermediate min* resultant to generate a final min* resultant based on the first input value and the second input value.

79. The method of claim 73, wherein:

the final log correction factor is a bit value of either a 0 or a 1 as defined by a single bit of precision.

80. The method of claim 73, wherein:

the method is performed within a decoder that is operable to decode an LDPC (Low Density Parity Check) coded signal.

81. The method of claim 73, wherein:

the method is performed within a decoder that is operable to decode a turbo coded signal or a TTCM (Turbo Trellis Coded Modulation) coded signal.

82. The method of claim 73, wherein:

the method is performed within a decoder that is operable to decode a coded signal;

the decoder is implemented within a communication device; and

the communication device is implemented within at least one of a cable television distribution system, a satellite communication system, an HDTV (High Definition Television) communication system, a cellular communication system, a microwave communication system, a point-to-point communication system, a uni-directional communication system, a bi-directional communication system, a one to many communication system, a fiber-optic communication system, a WLAN (Wireless Local Area Network) communication system, and a DSL (Digital Subscriber Line) communication system.

83. A method for performing max* (max star) processing, the method comprising:

during a first time period;

calculating a first plurality of LSBs (Least Significant Bits) of a difference between a first input value and a second input value;

during a second time period;

calculating a second plurality of LSBs of the difference between the first input value and the second input value;

determining a first log correction factor based on the first plurality of LSBs of the difference;

determining a second log correction factor based on the first plurality of LSBs of the difference;

during a third time period;

selecting either the first log correction factor or the second log correction factor as being a final log correction value based on an MSB (Most Significant Bit) of the second plurality of LSBs of the difference; and

selecting a maximum input value from among the first input value and the second input value based on an MSB of the difference; and

wherein;

the first input value is a finite precision number A;

the second input value is a finite precision number B;

in accordance with min* processing, the minimum input value is A or B; and

in accordance with min* processing, the final log correction factor is ln(1+e<sup>−

|A−

B|</sup>).

85. The method of claim 83, further comprising:

looking up the first log correction factor within a LUT (Look-Up Table) based on the first plurality of LSBs of the difference;

looking up the second log correction factor within the LUT based on the first plurality of LSBs of the difference;

wherein the LUT includes a plurality of first log correction factors and a plurality of second log correction factors defined as a function of first plurality of LSBs of the difference; and

wherein each log correction factor of the plurality of first log correction factors and a plurality of second log correction factors is bit value of either a 0 or a 1 as defined by a single bit of precision.

86. The method of claim 83, further comprising:

forcing the final log correction value to a predetermined value when each bit of the second plurality of LSBs of the difference is a 1 or when each bit of the second plurality of LSBs of the difference is a 0.

87. The method of claim 83, further comprising:

adding the final log correction factor to the maximum input value thereby generating a final max* resultant based on the first input value and the second input value.

88. The method of claim 83, further comprising:

adding the final log correction factor to the maximum input value thereby generating an intermediate max* resultant based on the first input value and the second input value; and

adding a constant value offset to the intermediate max* resultant to generate a final max* resultant based on the first input value and the second input value.

89. The method of claim 83, wherein:

the final log correction factor is a bit value of either a 0 or a 1 as defined by a single bit of precision.

90. The method of claim 83, wherein:

the method is performed within a decoder that is operable to decode an LDPC (Low Density Parity Check) coded signal.

91. The method of claim 83, wherein:

the method is performed within a decoder that is operable to decode a turbo coded signal or a TTCM (Turbo Trellis Coded Modulation) coded signal.

92. The method of claim 83, wherein:

the method is performed within a decoder that is operable to decode a coded signal;

the decoder is implemented within a communication device; and

the communication device is implemented within at least one of a cable television distribution system, a satellite communication system, an HDTV (High Definition Television) communication system, a cellular communication system, a microwave communication system, a point-to-point communication system, a uni-directional communication system, a bi-directional communication system, a one to many communication system, a fiber-optic communication system, a WLAN (Wireless Local Area Network) communication system, and a DSL (Digital Subscriber Line) communication system.