Memory hub bypass circuit and method

• US 7,415,567 B2
• Filed: 04/04/2006
• Issued: 08/19/2008
• Est. Priority Date: 08/16/2002
• Status: Expired due to Fees

• Current Assignee: Round Rock Research LLC
• Original Assignee: Micron Technology, Inc.
• Inventors: Jeddeloh, Joseph M.
• Primary Examiner(s): Peugh; Brian R.
• Application Number:
  US11/398,018
• Publication Number:
  US 20060174070A1
• Time in Patent Office: 868 Days
• Field of Search: 711/150, 711/152, 711/167, 711/168, 711/169, 711/5, 711/154
• US Class Current: 711/5
• CPC Class Codes: G06F 13/161 with latency improvement
• CPC Class Codes: G06F 13/1642 with request queuing
• CPC Class Codes: G06F 13/1684 using multiple buses

Abstract

A computer system and a method used to access data from a plurality of memory devices with a memory hub. The computer system includes a plurality of memory modules coupled to a memory hub controller. Each of the memory modules includes the memory hub and the plurality of memory devices. The memory hub includes a sequencer and a bypass circuit. When the memory hub is busy servicing one or more memory requests, the sequencer generates and couples the memory requests to the memory devices. When the memory hub is not busy servicing multiple memory requests, the bypass circuit generates and couples a portion of each the memory requests to the memory devices and the sequencer generates and couples the remaining portion of each of the memory requests to the memory devices.

Claims

1. A method of operating a memory hub coupled to a plurality of memory devices, the method comprising:

checking if the memory hub is servicing a memory request;

if the memory hub is not busy servicing a memory request, initially transmitting a portion of a received memory request from the memory hub to the memory devices, and scheduling the remaining portion of the received memory request for subsequent transmission from the memory hub to the memory devices; and

if the memory hub is busy servicing a memory request, scheduling the received memory request for subsequent transmission from the memory hub to the memory devices.

2. The method of claim 1 wherein the portion of the received memory request initially transmitted from the memory hub to the memory devices comprises a row address.

3. The method of claim 1, further comprising reformatting the received memory request before transmitting the memory request to the memory devices.